Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing

Oguz Meteer*, Marco Jan Gerrit Bekooij

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Fully integrated CMOS frequency-modulated continuous-wave radar ICs are under development, in which computing FFTs cost a significant amount of energy.

In this paper we introduce a power-efficient FFT solution which exploits that intermediate results of FFT computations typically have small amplitudes in FMCW radar systems. We propose using the sign-magnitude number representation combined with a custom, unsigned Booth multiplier that does not generate negative numbers internally, significantly decreasing switching activity.

RTL power-simulation results show up to 46.45% less power usage with our sign-magnitude radix-2 FFT implementation compared to a two’s complement design, while only having a 6.67% lower maximum clock speed.
Original languageEnglish
Title of host publication14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021
EditorsTomasz Kryjak, Andrea Pinna
Place of PublicationBudapest, Hungary
Pages52-59
Number of pages8
Edition14
DOIs
Publication statusPublished - 18 Jan 2021
Event14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021 - Virtual Event
Duration: 18 Jan 202120 Jan 2021
Conference number: 14
https://dasip2021.agh.edu.pl/

Workshop

Workshop14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021
Abbreviated titleDASIP 2021
CityVirtual Event
Period18/01/2120/01/21
Internet address

Fingerprint Dive into the research topics of 'Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing'. Together they form a unique fingerprint.

Cite this