Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing

Oguz  Meteer; Marco Jan Gerrit Bekooij

doi:10.1145/3441110.3441145

Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing

Oguz Meteer^*
, Marco Jan Gerrit Bekooij

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

76 Downloads (Pure)

Abstract

Fully integrated CMOS frequency-modulated continuous-wave radar ICs are under development, in which computing FFTs cost a significant amount of energy.

In this paper we introduce a power-efficient FFT solution which exploits that intermediate results of FFT computations typically have small amplitudes in FMCW radar systems. We propose using the sign-magnitude number representation combined with a custom, unsigned Booth multiplier that does not generate negative numbers internally, significantly decreasing switching activity.

RTL power-simulation results show up to 46.45% less power usage with our sign-magnitude radix-2 FFT implementation compared to a two’s complement design, while only having a 6.67% lower maximum clock speed.

Original language	English
Title of host publication	14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021
Editors	Tomasz Kryjak, Andrea Pinna
Place of Publication	Budapest, Hungary
Pages	52-59
Number of pages	8
Edition	14
ISBN (Electronic)	9781450389013
DOIs	https://doi.org/10.1145/3441110.3441145
Publication status	Published - 1 Feb 2021
Event	14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021 - Virtual Event Duration: 18 Jan 2021 → 20 Jan 2021 Conference number: 14 https://dasip2021.agh.edu.pl/

Publication series

Name	ACM International Conference Proceeding Series

Workshop

Workshop	14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021
Abbreviated title	DASIP 2021
City	Virtual Event
Period	18/01/21 → 20/01/21
Internet address	https://dasip2021.agh.edu.pl/

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10.1145/3441110.3441145

3441110.3441145Final published version, 830 KB

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@inproceedings{a1ddb2d6778f47d5a5dbf7bf242984f0,

title = "Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing",

abstract = "Fully integrated CMOS frequency-modulated continuous-wave radar ICs are under development, in which computing FFTs cost a significant amount of energy. In this paper we introduce a power-efficient FFT solution which exploits that intermediate results of FFT computations typically have small amplitudes in FMCW radar systems. We propose using the sign-magnitude number representation combined with a custom, unsigned Booth multiplier that does not generate negative numbers internally, significantly decreasing switching activity. RTL power-simulation results show up to 46.45\% less power usage with our sign-magnitude radix-2 FFT implementation compared to a two{\textquoteright}s complement design, while only having a 6.67\% lower maximum clock speed.",

author = "Oguz Meteer and Bekooij, \{Marco Jan Gerrit\}",

note = "Funding Information: This work is part of the research program Perspectief ZERO with project number P15-06 Project 3, which is (partly) financed by the Dutch Research Council (NWO). Publisher Copyright: {\textcopyright} 2021 ACM.; 14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021, DASIP 2021 ; Conference date: 18-01-2021 Through 20-01-2021",

year = "2021",

month = feb,

day = "1",

doi = "10.1145/3441110.3441145",

language = "English",

isbn = "9781450389013",

series = "ACM International Conference Proceeding Series",

pages = "52--59",

editor = "Tomasz Kryjak and Andrea Pinna",

booktitle = "14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021",

edition = "14",

url = "https://dasip2021.agh.edu.pl/",

}

Meteer, O & Bekooij, MJG 2021, Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing. in T Kryjak & A Pinna (eds), 14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021. 14 edn, 3441145, ACM International Conference Proceeding Series, Budapest, Hungary, pp. 52-59, 14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021, Virtual Event, 18/01/21. https://doi.org/10.1145/3441110.3441145

Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing. / Meteer, Oguz ; Bekooij, Marco Jan Gerrit.
14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021. ed. / Tomasz Kryjak; Andrea Pinna. 14. ed. Budapest, Hungary, 2021. p. 52-59 3441145 (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Y1 - 2021/2/1

N2 - Fully integrated CMOS frequency-modulated continuous-wave radar ICs are under development, in which computing FFTs cost a significant amount of energy. In this paper we introduce a power-efficient FFT solution which exploits that intermediate results of FFT computations typically have small amplitudes in FMCW radar systems. We propose using the sign-magnitude number representation combined with a custom, unsigned Booth multiplier that does not generate negative numbers internally, significantly decreasing switching activity. RTL power-simulation results show up to 46.45% less power usage with our sign-magnitude radix-2 FFT implementation compared to a two’s complement design, while only having a 6.67% lower maximum clock speed.

AB - Fully integrated CMOS frequency-modulated continuous-wave radar ICs are under development, in which computing FFTs cost a significant amount of energy. In this paper we introduce a power-efficient FFT solution which exploits that intermediate results of FFT computations typically have small amplitudes in FMCW radar systems. We propose using the sign-magnitude number representation combined with a custom, unsigned Booth multiplier that does not generate negative numbers internally, significantly decreasing switching activity. RTL power-simulation results show up to 46.45% less power usage with our sign-magnitude radix-2 FFT implementation compared to a two’s complement design, while only having a 6.67% lower maximum clock speed.

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DO - 10.1145/3441110.3441145

M3 - Conference contribution

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BT - 14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021

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T2 - 14th Workshop on Design and Architectures for Signal and Image Processing, DASIP 2021

Y2 - 18 January 2021 through 20 January 2021

ER -

Low-Power Sign-Magnitude FFT Design for FMCW Radar Signal Processing

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