Low-temperature fabricated TFTs on polysilicon stripes

Ihor Brunets, Jisk Holleman, Alexeij Y. Kovalgin, Arjen Boogaard, Jurriaan Schmitz

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    16 Citations (Scopus)
    172 Downloads (Pure)


    This paper presents a novel approach to make highperformance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/V • s (NMOS) and 128 cm2/V • s (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration.
    Original languageEnglish
    Pages (from-to)1637-1644
    Number of pages8
    JournalIEEE Transactions on Electron Devices
    Issue number8
    Publication statusPublished - Aug 2009


    • Grain boundary
    • Thin-film transistor (TFT)
    • Laser annealing
    • Above integrated circuit (IC)
    • Polycrystalline silicon
    • 3-D integration
    • SC-ICF: Integrated Circuit Fabrication


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