Low temperature pure boron layer deposition for silicon diode and micromachining applications

This thesis was focused on further explorations to extend the applicability and availability of PureB technology. In particular, B-layer depositions at temperatures below 500℃ were developed to enhance the CMOS compatibility. Several types of deposition equipment in different configurations were used to fabricate B-layers on Si, and the influence of deposition conditions were evaluated with respect to the properties of the B-layer itself as well as to the integration of the layer in PureB diodes.
For the B-layer development, non-metalized electrical test structures proved very useful in that they allowed an electrical evaluation of the as-deposited layers in fast turnaround time process flows. The B-Si interfacial sheet resistance (Rsh) and the electron current (Ie) in the PureB diodes were routinely monitored. Both parameters are important for assessing whether the B-layer would have suitable electrical properties for use in a specific PureB diode application.
The Si anisotropic etchants, TMAH/KOH, were successfully used to evaluate the compactness of thin B-layers grown on Si under different process conditions. It was clearly shown that as the CVD layers were deposited at higher temperatures, better uniformity, selectivity and compactness, were achieved. At low temperatures, thicker layers were needed to overgrow weak spots in the layer structuring.
PureB diodes were fabricated at temperatures down to 200℃ where Rsh and Ie were high. At this temperature, and also at 250℃, the thickness of the layer saturated at 1 nm to 1.5 nm. However, at 250 ℃ the I-V characteristics were similar to those of thick layers grown at 400 ℃, showing that the B-coverage obtained at the lowest temperature was quite good even though vertical growth was not obtained. To enable deposition below 200 ℃, MBE B-deposition was investigated. Even at room temperature, PureB diodes were fabricated, albeit with very high Rsh and Ie. At 300℃ to 400℃, the MBE results were very similar to the CVD results. The furnace ULPCVD system enabled batch processing, but with poorer selectivity. For 10-nm-thick B-deposition an electrically connected layer was deposited on the oxide.
While requirements for low series resistance and high transmissivity mainly will dictate that the B-layers in PureB (photo)diodes be but a few nanometers thick, for masking and membrane fabrication much thicker layers can be desirable. At 400℃ the Picosun layers were slightly tensile and several millimeter large membranes with tens-of-nanometer to a micrometer thickness were successfully fabricated.