Managing Verification Activities Using SVM

Bill Aldrich, Ansgar Fehnker, Peter H. Feiler, Zhi Han, Bruce H. Krogh, Eric Lim, Shiva Sivashankar

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)


SVM (System Verification Manager) manages the application of verification methods for model-based development of embedded systems by providing integrated representations of requirements, system architecture, models and verification methods. Developed in Java within MATLAB®, SVM supports all types of tools for modelling and verification through an extensible framework of data and coding structures. This paper presents the main features of SVM and illustrates its application to embedded control and signal processing systems.
Original languageEnglish
Title of host publicationFormal Methods and Software Engineering
Subtitle of host publication6th International Conference on Formal Engineering Methods, ICFEM 2004, Seattle, WA, USA, November 8-12, 2004, Proceedings
EditorsJim Davies, Wolfram Schulte, Michael Barnett
Number of pages15
ISBN (Electronic)978-3-540-30482-1
ISBN (Print)978-3-540-23841-6
Publication statusPublished - 2004
Externally publishedYes
Event6th International Conference on Formal Engineering Methods, ICFEM 2004 - Seattle, United States
Duration: 8 Nov 200412 Nov 2004
Conference number: 6

Publication series

NameLecture Notes in Computer Science


Conference6th International Conference on Formal Engineering Methods, ICFEM 2004
Abbreviated titleICFEM 2004
CountryUnited States

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