Mapping a mathematical expression onto a Montium ALU using GNU Bison

M.A.J. Rosien; Gerardus Johannes Maria Smit

Mapping a mathematical expression onto a Montium ALU using GNU Bison

M.A.J. Rosien, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

The Montium processing tile [1], [4] contains a number of complex ALUs which can perform many different operations in many different ways. In the Chameleon tool flow [2], it is necessary to automatically determine whether a certain mathematical expression can be mapped onto an ALU and to automatically generate an ALU configuration for this expression. This paper describes how the parser generator GNU Bison [5] is used to determine whether a mapping is possible and how Generalized LR Parsing [6] is used to cope with ambiguities and to generate all possible mappings of a specific expression onto an ALU.

Original language	Undefined
Title of host publication	5th PROGRESS Symposium on Embedded Systems
Publisher	STW
Pages	170-180
Number of pages	11
ISBN (Print)	90-73461-41-3
Publication status	Published - Oct 2004
Event	5th PROGRESS Symposium on Embedded Systems 2004 - Nieuwegein, Netherlands Duration: 20 Oct 2004 → 20 Oct 2004 Conference number: 5

Publication series

Name
Publisher	STW Technology Foundation

Conference

Conference	5th PROGRESS Symposium on Embedded Systems 2004
Abbreviated title	PROGRESS
Country	Netherlands
City	Nieuwegein
Period	20/10/04 → 20/10/04

Keywords

METIS-221672
CAES-EEA: Efficient Embedded Architectures
EWI-1491
IR-49386

Access to Document

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Cite this

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title = "Mapping a mathematical expression onto a Montium ALU using GNU Bison",

abstract = "The Montium processing tile [1], [4] contains a number of complex ALUs which can perform many different operations in many different ways. In the Chameleon tool flow [2], it is necessary to automatically determine whether a certain mathematical expression can be mapped onto an ALU and to automatically generate an ALU configuration for this expression. This paper describes how the parser generator GNU Bison [5] is used to determine whether a mapping is possible and how Generalized LR Parsing [6] is used to cope with ambiguities and to generate all possible mappings of a specific expression onto an ALU.",

keywords = "METIS-221672, CAES-EEA: Efficient Embedded Architectures, EWI-1491, IR-49386",

author = "M.A.J. Rosien and Smit, {Gerardus Johannes Maria}",

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year = "2004",

month = oct,

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publisher = "STW",

pages = "170--180",

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AU - Rosien, M.A.J.

AU - Smit, Gerardus Johannes Maria

N1 - Conference code: 5

PY - 2004/10

Y1 - 2004/10

N2 - The Montium processing tile [1], [4] contains a number of complex ALUs which can perform many different operations in many different ways. In the Chameleon tool flow [2], it is necessary to automatically determine whether a certain mathematical expression can be mapped onto an ALU and to automatically generate an ALU configuration for this expression. This paper describes how the parser generator GNU Bison [5] is used to determine whether a mapping is possible and how Generalized LR Parsing [6] is used to cope with ambiguities and to generate all possible mappings of a specific expression onto an ALU.

AB - The Montium processing tile [1], [4] contains a number of complex ALUs which can perform many different operations in many different ways. In the Chameleon tool flow [2], it is necessary to automatically determine whether a certain mathematical expression can be mapped onto an ALU and to automatically generate an ALU configuration for this expression. This paper describes how the parser generator GNU Bison [5] is used to determine whether a mapping is possible and how Generalized LR Parsing [6] is used to cope with ambiguities and to generate all possible mappings of a specific expression onto an ALU.

KW - METIS-221672

KW - CAES-EEA: Efficient Embedded Architectures

KW - EWI-1491

KW - IR-49386

M3 - Conference contribution

SN - 90-73461-41-3

SP - 170

EP - 180

BT - 5th PROGRESS Symposium on Embedded Systems

PB - STW

Y2 - 20 October 2004 through 20 October 2004

ER -