Mapping and Scheduling of Directed Acyclic Graphs on An FPFA Tile

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    An architecture for a hand-held multimedia device requires components that are energy-efficient, flexible, and provide high performance. In the CHAMELEON [4] project we develop a coarse grained reconfigurable device for DSP-like algorithms, the so-called Field Programmable Function Array (FPFA). The FPFA devices are reminiscent to FPGAs, but with a matrix of Processing Parts (PP) instead of CLBs. The design of the FPFA focuses on: (1) Keeping each PP small to maximize the number of PPs that can fit on a chip; (2) providing sufficient flexibility; (3) Low energy consumption; (4) Exploiting the maximum amount of parallelism; (5) A strong support tool for FPFA-based applications. The challenge in providing compiler support for the FPFA-based design stems from the flexibility of the FPFA structure. If we do not use the characteristics of the FPFA structure properly, the advantages of an FPFA may become its disadvantages. The GECKO1project focuses on this problem. In this paper, we present a mapping and scheduling scheme for applications running on one FPFA tile. Applications are written in C and C code is translated to a Directed Acyclic Graphs (DAG) [4]. This scheme can map a DAG directly onto the reconfigurable PPs of an FPFA tile. It tries to achieve low power consumption by exploiting locality of reference and high performance by exploiting maximum parallelism.
    Original languageUndefined
    Number of pages9
    Publication statusPublished - Oct 2002
    Event3rd PROGRESS Workshop on Embedded Systems 2002 - Utrecht, Netherlands
    Duration: 24 Oct 200224 Oct 2002
    Conference number: 3


    Workshop3rd PROGRESS Workshop on Embedded Systems 2002
    Abbreviated titlePROGRESS


    • CAES-EEA: Efficient Embedded Architectures
    • IR-66351
    • EWI-6912

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