Mapping Applications to an FPFA Tile

M.A.J. Rosien, Y. Guo, Gerardus Johannes Maria Smit, Th. Krol

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    3 Citations (Scopus)
    27 Downloads (Pure)


    This paper introduces a transformational design method which can be used to map code written in ahhigh level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Datafow graph (CDFG), which is minimized using a set of behaviour preserving transformations such as dependency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.
    Original languageEnglish
    Title of host publicationProceedings of DATE 2003
    Place of PublicationMunich
    PublisherIEEE Computer Society
    Number of pages2
    ISBN (Print)0-7695-1870-2
    Publication statusPublished - Mar 2003
    Event2003 Design, Automation and Test in Europe Conference and Exposition, DATE 2003 - Munich, Germany
    Duration: 3 Mar 20037 Mar 2003


    Conference2003 Design, Automation and Test in Europe Conference and Exposition, DATE 2003
    Abbreviated titleDATE


    • CAES-EEA: Efficient Embedded Architectures
    • EWI-1517
    • IR-46339
    • METIS-214675


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