Mapping the SISO module of the Turbo Decoder to a FPFA

Gerardus Johannes Maria Smit; P.M. Heysters; Paul J.M. Havinga; L.T. Smit; John Dilessen; Jos Huisken

Mapping the SISO module of the Turbo Decoder to a FPFA

Gerardus Johannes Maria Smit, P.M. Heysters, Paul J.M. Havinga, L.T. Smit, John Dilessen, Jos Huisken

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.

Original language	Undefined
Title of host publication	Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000)
Place of Publication	Delft
Pages	165-172
Number of pages	8
Publication status	Published - Nov 2000
Event	2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000 - Delft, Netherlands Duration: 9 Nov 2000 → 10 Nov 2000 Conference number: 2

Conference

Conference	2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000
Abbreviated title	MMSA
Country/Territory	Netherlands
City	Delft
Period	9/11/00 → 10/11/00

Keywords

EWI-1530
CAES-EEA: Efficient Embedded Architectures
METIS-114196
IR-17301
CAES-PS: Pervasive Systems

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Cite this

@inproceedings{ab4377c9b2fd48399d46eeac074535cf,

title = "Mapping the SISO module of the Turbo Decoder to a FPFA",

abstract = "In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.",

keywords = "EWI-1530, CAES-EEA: Efficient Embedded Architectures, METIS-114196, IR-17301, CAES-PS: Pervasive Systems",

author = "Smit, {Gerardus Johannes Maria} and P.M. Heysters and Havinga, {Paul J.M.} and L.T. Smit and John Dilessen and Jos Huisken",

note = "Imported from CHAMELEON.xml; 2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000 ; Conference date: 09-11-2000 Through 10-11-2000",

year = "2000",

month = nov,

language = "Undefined",

isbn = "90-9014360-2",

pages = "165--172",

booktitle = "Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000)",

}

Smit, GJM, Heysters, PM, Havinga, PJM, Smit, LT, Dilessen, J & Huisken, J 2000, Mapping the SISO module of the Turbo Decoder to a FPFA. in Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000). Delft, pp. 165-172, 2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000, Delft, Netherlands, 9/11/00.

Mapping the SISO module of the Turbo Decoder to a FPFA. / Smit, Gerardus Johannes Maria; Heysters, P.M.; Havinga, Paul J.M. et al.
Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000). Delft, 2000. p. 165-172.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Mapping the SISO module of the Turbo Decoder to a FPFA

AU - Smit, Gerardus Johannes Maria

AU - Heysters, P.M.

AU - Havinga, Paul J.M.

AU - Smit, L.T.

AU - Dilessen, John

AU - Huisken, Jos

N1 - Conference code: 2

PY - 2000/11

Y1 - 2000/11

N2 - In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.

AB - In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.

KW - EWI-1530

KW - CAES-EEA: Efficient Embedded Architectures

KW - METIS-114196

KW - IR-17301

KW - CAES-PS: Pervasive Systems

M3 - Conference contribution

SN - 90-9014360-2

SP - 165

EP - 172

BT - Proceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000)

CY - Delft

T2 - 2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000

Y2 - 9 November 2000 through 10 November 2000

ER -