Mapping the SISO module of the Turbo Decoder to a FPFA

Gerardus Johannes Maria Smit, P.M. Heysters, Paul J.M. Havinga, L.T. Smit, John Dilessen, Jos Huisken

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    Abstract

    In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA.
    Original languageUndefined
    Title of host publicationProceedings of Second international symposium on Mobile Multimedia Systems & Applications (MMSA2000)
    Place of PublicationDelft
    Pages165-172
    Number of pages8
    Publication statusPublished - Nov 2000
    Event2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000 - Delft, Netherlands
    Duration: 9 Nov 200010 Nov 2000
    Conference number: 2

    Conference

    Conference2nd International Symposium on Mobile Multimedia Systems & Applications, MMSA 2000
    Abbreviated titleMMSA
    CountryNetherlands
    CityDelft
    Period9/11/0010/11/00

    Keywords

    • EWI-1530
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-114196
    • IR-17301
    • CAES-PS: Pervasive Systems

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