Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

G.K. Rauwerda, P.M. Heysters, Gerardus Johannes Maria Smit

    Research output: Contribution to journalArticleAcademicpeer-review

    22 Citations (Scopus)
    129 Downloads (Pure)

    Abstract

    Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.
    Original languageUndefined
    Pages (from-to)263-282
    Number of pages20
    JournalJournal of supercomputing
    Volume30
    Issue number3
    DOIs
    Publication statusPublished - Dec 2004

    Keywords

    • EWI-1481
    • METIS-220634
    • CAES-EEA: Efficient Embedded Architectures
    • IR-48856

    Cite this

    @article{e7a6bdacc13943e8aab4500b1439a6bc,
    title = "Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture",
    abstract = "Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.",
    keywords = "EWI-1481, METIS-220634, CAES-EEA: Efficient Embedded Architectures, IR-48856",
    author = "G.K. Rauwerda and P.M. Heysters and Smit, {Gerardus Johannes Maria}",
    note = "Imported from CHAMELEON.xml",
    year = "2004",
    month = "12",
    doi = "10.1023/B:SUPE.0000045212.45532.13",
    language = "Undefined",
    volume = "30",
    pages = "263--282",
    journal = "Journal of supercomputing",
    issn = "0920-8542",
    publisher = "Springer",
    number = "3",

    }

    Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture. / Rauwerda, G.K.; Heysters, P.M.; Smit, Gerardus Johannes Maria.

    In: Journal of supercomputing, Vol. 30, No. 3, 12.2004, p. 263-282.

    Research output: Contribution to journalArticleAcademicpeer-review

    TY - JOUR

    T1 - Mapping Wireless Communication Algorithms onto a Reconfigurable Architecture

    AU - Rauwerda, G.K.

    AU - Heysters, P.M.

    AU - Smit, Gerardus Johannes Maria

    N1 - Imported from CHAMELEON.xml

    PY - 2004/12

    Y1 - 2004/12

    N2 - Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.

    AB - Future mobile communication systems have to be flexible while adapting to environmental conditions and user demands. These systems also have to be energy-efficient as they are used in battery-operated terminals. We expect that heterogeneous reconfigurable hardware can overcome the contradicting requirements in flexibility, energy-efficiency and performance. A coarse-grain reconfigurable processor, called MONTIUM, is presented. An overview of a wireless LAN communication system, HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in heterogeneous reconfigurable hardware are discussed. Performance figures of the implemented HiperLAN/2 baseband processing in the MONTIUM architecture are presented. The required performance can be obtained at low clock frequencies with small configuration overhead. The flexibility of the MONTIUM is shown, as the baseband processing of both HiperLAN/2 and Bluetooth is implemented on the same architecture.

    KW - EWI-1481

    KW - METIS-220634

    KW - CAES-EEA: Efficient Embedded Architectures

    KW - IR-48856

    U2 - 10.1023/B:SUPE.0000045212.45532.13

    DO - 10.1023/B:SUPE.0000045212.45532.13

    M3 - Article

    VL - 30

    SP - 263

    EP - 282

    JO - Journal of supercomputing

    JF - Journal of supercomputing

    SN - 0920-8542

    IS - 3

    ER -