Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.
|Other||2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02|
|Period||24/06/02 → 27/06/02|
- CAES-EEA: Efficient Embedded Architectures
- CAES-PS: Pervasive Systems