@inproceedings{fc2b7beeca984ef5a28d49f1d6105873,
title = "Max-Log-MAP Mapping on an FPFA",
abstract = "Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.",
keywords = "METIS-210499, CAES-EEA: Efficient Embedded Architectures, CAES-PS: Pervasive Systems, EWI-896, IR-38403",
author = "P.M. Heysters and L.T. Smit and Smit, {Gerardus Johannes Maria} and Havinga, {Paul J.M.}",
note = "Imported from DIES; null ; Conference date: 24-06-2002 Through 27-06-2002",
year = "2002",
month = jun,
language = "Undefined",
isbn = "1-892512-96-3",
publisher = "CSREA Press",
pages = "90--96",
booktitle = "IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002",
}