Max-Log-MAP Mapping on an FPFA

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    Abstract

    Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.
    Original languageUndefined
    Title of host publicationIInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002
    Place of PublicationLas Vegas
    PublisherCSREA Press
    Pages90-96
    Number of pages7
    ISBN (Print)1-892512-96-3
    Publication statusPublished - Jun 2002
    Event2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02 - Las Vegas, United States
    Duration: 24 Jun 200227 Jun 2002

    Publication series

    Name
    PublisherCSREA Press

    Other

    Other2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02
    Abbreviated titleERSA
    CountryUnited States
    CityLas Vegas
    Period24/06/0227/06/02

    Keywords

    • METIS-210499
    • CAES-EEA: Efficient Embedded Architectures
    • CAES-PS: Pervasive Systems
    • EWI-896
    • IR-38403

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