Max-Log-MAP Mapping on an FPFA

P.M. Heysters; L.T. Smit; Gerardus Johannes Maria Smit; Paul J.M. Havinga

Max-Log-MAP Mapping on an FPFA

P.M. Heysters
, L.T. Smit
, Gerardus Johannes Maria Smit
, Paul J.M. Havinga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

464 Downloads (Pure)

Abstract

Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.

Original language	Undefined
Title of host publication	IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002
Place of Publication	Las Vegas
Publisher	CSREA Press
Pages	90-96
Number of pages	7
ISBN (Print)	1-892512-96-3
Publication status	Published - Jun 2002
Event	2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02 - Las Vegas, United States Duration: 24 Jun 2002 → 27 Jun 2002

Publication series

Name
Publisher	CSREA Press

Other

Other	2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02
Abbreviated title	ERSA
Country/Territory	United States
City	Las Vegas
Period	24/06/02 → 27/06/02

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

METIS-210499
CAES-EEA: Efficient Embedded Architectures
CAES-PS: Pervasive Systems
EWI-896
IR-38403

Access to Document

heysters_ersa02

http://eprints.eemcs.utwente.nl/secure2/896/01/heysters_ersa02.pdf

Cite this

@inproceedings{fc2b7beeca984ef5a28d49f1d6105873,

title = "Max-Log-MAP Mapping on an FPFA",

abstract = "Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.",

keywords = "METIS-210499, CAES-EEA: Efficient Embedded Architectures, CAES-PS: Pervasive Systems, EWI-896, IR-38403",

author = "P.M. Heysters and L.T. Smit and Smit, \{Gerardus Johannes Maria\} and Havinga, \{Paul J.M.\}",

note = "Imported from DIES; 2002 International Conference on Engineering of Reconfigurable Systems \& Algorithms, ERSA '02 ; Conference date: 24-06-2002 Through 27-06-2002",

year = "2002",

month = jun,

language = "Undefined",

isbn = "1-892512-96-3",

publisher = "CSREA Press",

pages = "90--96",

booktitle = "IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002",

}

Heysters, PM, Smit, LT, Smit, GJM & Havinga, PJM 2002, Max-Log-MAP Mapping on an FPFA. in IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002. CSREA Press, Las Vegas, pp. 90-96, 2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02, Las Vegas, Nevada, United States, 24/06/02. <http://eprints.eemcs.utwente.nl/secure2/896/01/heysters_ersa02.pdf>

TY - GEN

T1 - Max-Log-MAP Mapping on an FPFA

AU - Heysters, P.M.

AU - Smit, L.T.

AU - Smit, Gerardus Johannes Maria

AU - Havinga, Paul J.M.

N1 - Imported from DIES

PY - 2002/6

Y1 - 2002/6

N2 - Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.

AB - Computational-intensive parts of algorithms often execute energy-inefficient on general-purpose processors. Reconfigurable hardware could improve the energy efficiency while maintaining a sufficient level of flexibility. In a case study, the computational-intensive Max-log-MAP algorithm of Turbo decoding is mapped on the Field Programmable Function Array (FPFA). The FPFA is an architecture for a dynamically reconfigurable device that consists of a matrix of reconfigurable processor tiles.

KW - METIS-210499

KW - CAES-EEA: Efficient Embedded Architectures

KW - CAES-PS: Pervasive Systems

KW - EWI-896

KW - IR-38403

M3 - Conference contribution

SN - 1-892512-96-3

SP - 90

EP - 96

BT - IInternational Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2002

PB - CSREA Press

CY - Las Vegas

T2 - 2002 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '02

Y2 - 24 June 2002 through 27 June 2002

ER -