MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing

Anuradha C. Ranasinghe*, Sabih H. Gerez

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vth operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vth level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.
Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020
PublisherIEEE
Pages96-104
Number of pages9
ISBN (Electronic)978-1-7281-9710-4
ISBN (Print)978-1-7281-9710-4
DOIs
Publication statusPublished - 21 Dec 2020
Event38th IEEE International Conference on Computer Design, ICCD 2020 - Virtual Event
Duration: 18 Oct 202021 Oct 2020
Conference number: 38

Conference

Conference38th IEEE International Conference on Computer Design, ICCD 2020
Abbreviated titleICCD 2020
CityVirtual Event
Period18/10/2021/10/20

Keywords

  • Alternative Logic Styles
  • Inverse Narrow Width Effect
  • Near/Sub-Vth
  • Parasitic Reduction
  • ULV

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