MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing

Anuradha C. Ranasinghe; Sabih H. Gerez

doi:10.1109/ICCD50377.2020.00032

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing

Anuradha C. Ranasinghe^*, Sabih H. Gerez

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

111 Downloads (Pure)

Abstract

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vth operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vth level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

Original language	English
Title of host publication	Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020
Publisher	IEEE
Pages	96-104
Number of pages	9
ISBN (Electronic)	978-1-7281-9710-4
ISBN (Print)	978-1-7281-9710-4
DOIs	https://doi.org/10.1109/ICCD50377.2020.00032
Publication status	Published - 21 Dec 2020
Event	38th IEEE International Conference on Computer Design, ICCD 2020 - Virtual Event Duration: 18 Oct 2020 → 21 Oct 2020 Conference number: 38

Conference

Conference	38th IEEE International Conference on Computer Design, ICCD 2020
Abbreviated title	ICCD 2020
City	Virtual Event
Period	18/10/20 → 21/10/20

Keywords

Alternative Logic Styles
Inverse Narrow Width Effect
Near/Sub-Vth
Parasitic Reduction
ULV
22/2 OA procedure

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ICCD50377.2020.00032

10.1109_iccd50377.2020.00032Final published version, 1.15 MBLicence: Taverne

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title = "MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing",

abstract = "This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vth operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vth level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.",

keywords = "Alternative Logic Styles, Inverse Narrow Width Effect, Near/Sub-Vth, Parasitic Reduction, ULV, 22/2 OA procedure",

author = "Ranasinghe, {Anuradha C.} and Gerez, {Sabih H.}",

note = "Funding Information: ACKNOWLEDGMENT The research reported in this paper is supported by the Dutch NWO Applied and Engineering Sciences program ZERO: Towards Energy Autonomous Systems for IoT and by Dialog Semiconductor B.V., The Netherlands. Publisher Copyright: {\textcopyright} 2020 IEEE.; 38th IEEE International Conference on Computer Design, ICCD 2020, ICCD 2020 ; Conference date: 18-10-2020 Through 21-10-2020",

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month = dec,

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doi = "10.1109/ICCD50377.2020.00032",

language = "English",

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pages = "96--104",

booktitle = "Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020",

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Ranasinghe, AC & Gerez, SH 2020, MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing. in Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020., 9283594, IEEE, pp. 96-104, 38th IEEE International Conference on Computer Design, ICCD 2020, Virtual Event, 18/10/20. https://doi.org/10.1109/ICCD50377.2020.00032

MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing. / Ranasinghe, Anuradha C.; Gerez, Sabih H.
Proceedings - 2020 IEEE 38th International Conference on Computer Design, ICCD 2020. IEEE, 2020. p. 96-104 9283594.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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PY - 2020/12/21

Y1 - 2020/12/21

N2 - This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vth operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vth level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

AB - This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- Vth operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- Vth level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

KW - Alternative Logic Styles

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KW - Near/Sub-Vth

KW - Parasitic Reduction

KW - ULV

KW - 22/2 OA procedure

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MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-Vth Computing

Abstract

Conference

Keywords

UN SDGs

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