Method and circuitry for CMOS transconductor linearization

H. Kundur Subramaniyan (Inventor), Eric A.M. Klumperink (Inventor), Srinivasan Venkatesh (Inventor), Ali Kiaei (Inventor), Bram Nauta (Inventor)

    Research output: Patent

    8 Downloads (Pure)

    Abstract

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second­ order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.
    Original languageEnglish
    Patent numberUS9531335 (B2)
    Priority date5/08/15
    Publication statusPublished - 27 Dec 2016

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  • Cite this

    Kundur Subramaniyan, H., Klumperink, E. A. M., Venkatesh, S., Kiaei, A., & Nauta, B. (2016). Method and circuitry for CMOS transconductor linearization. (Patent No. US9531335 (B2)).