Minimizing scrubbing effort through automatic netlist partitioning and floorplanning

Bernhard Schmidt, Daniel Ziener, Jürgen Teich

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)
1 Downloads (Pure)

Abstract

Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.

Original languageEnglish
Title of host publicationProceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014
PublisherIEEE Computer Society
Pages299-304
Number of pages6
ISBN (Electronic)9780769552088
DOIs
Publication statusPublished - 27 Nov 2014
Externally publishedYes
Event28th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014 - Phoenix, United States
Duration: 19 May 201423 May 2014
Conference number: 28

Conference

Conference28th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014
Abbreviated titleIPDPSW 2014
CountryUnited States
CityPhoenix
Period19/05/1423/05/14

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