Minority carrier tunneling and stress-induced leakage current for p+ gate MOS capacitors with poly-Si and poly-Si0.7Ge0.3 gate material

V.E. Houtsma, J. Holleman, C. Salm, I.R. de Haan, J. Schmitz, F.P. Widdershoven, P.H. Woerlee

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    6 Citations (Scopus)
    18 Downloads (Pure)


    In this paper the I-V conduction mechanism for gate injection (-Vg), Stress-Induced Leakage Current(SILC) characteristics and time-to-breakdown(tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discussed.

    Original languageEnglish
    Title of host publicationInternational Electron Devices Meeting 1999
    Subtitle of host publicationWashington, DC, December 5-8, 1999, IEDM technical digest
    Place of PublicationPiscataway, NJ
    Number of pages4
    ISBN (Electronic)0-7803-5413-3
    ISBN (Print)0-7803-5410-9, 0-7803-5411-7
    Publication statusPublished - Dec 1999
    Event1999 IEEE International Devices Meeting (IEDM) - Washington, United States
    Duration: 5 Dec 19998 Dec 1999

    Publication series

    NameInternational Electron Devices Meeting, IEDM Technical Digest
    ISSN (Print)0163-1918


    Conference1999 IEEE International Devices Meeting (IEDM)
    Abbreviated titleIEDM 1999
    CountryUnited States

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