Modelling and mitigation of soft-errors in CMOS processors

The topic of this thesis is about soft-errors in digital systems. Different aspects of soft-errors have been addressed here, including an accurate simulation model to emulate soft-errors in a gate-level net list, a simulation framework to study the impact of soft-errors in a VHDL design and an efficient architecture to minimize the impact of soft-errors in a DSP processor. The first two chapters of this thesis introduce the basic knowledge with regard to soft-errors. Chapter three introduces a simulation framework to study the impact of soft-errors in complex digital systems modelled in VHDL language. This framework has been introduced to resolve the enormous CPU time typically required in simulation-based soft-error experiments. Chapter four introduces two realistic simulation models that can emulate the impact of soft-errors in a 45-nm CMOS technology node at a gate level. One of the determination approaches has been extracted from radiation testing along with using a transistor-level soft-error analysis tool. Another approach has been developed by analysing the behaviour of soft-errors in a 45-nm CMOS technology node. In chapter 5, some unique features of DSP processors have been exploited to introduce a low-overhead soft-error mitigation architecture to minimize the impact of soft-errors in a DSP processor. This mitigation technique concerns unstructured parts of a processor (such as the control unit and data path). The unique features of DSP processors are existence of several functional units, a limited number of different opcodes in each functional unit and also highly-repetitive instruction flow in a DSP workload. Moreover, the mitigation method which has been developed for a single core has been applied to a multi-core environment in chapter 6 to propose a soft-error mitigation technique for multi-core architectures. Overall, based on simulated data and experiments, this thesis proposes a methodology to investigate the impact of soft-errors during the design phase of a digital system.