This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.
de Wolf, M. A. R. C., De Keukeleire, C., de Wolf, M., van Hove, H., & Witters, J. (1998). Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors. Microelectronics reliability, 38(6-8), 1097-1101. https://doi.org/10.1016/S0026-2714(98)00115-2