Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

M.A.R.C. de Wolf, Catherine De Keukeleire, Marc de Wolf, Hugo van Hove, Johan Witters

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    Abstract

    This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.
    Original languageUndefined
    Pages (from-to)1097-1101
    JournalMicroelectronics reliability
    Volume38
    Issue number6-8
    DOIs
    Publication statusPublished - 1998

    Keywords

    • IR-73812

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