Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

M.A.R.C. de Wolf; Catherine De Keukeleire; Marc de Wolf; Hugo van Hove; Johan Witters

doi:10.1016/S0026-2714(98)00115-2

Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

M.A.R.C. de Wolf
, Catherine De Keukeleire
, Marc de Wolf
, Hugo van Hove
, Johan Witters

Research output: Contribution to journal › Article › Academic

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4 Downloads (Pure)

Abstract

This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.

Original language	English
Pages (from-to)	1097-1101
Journal	Microelectronics reliability
Volume	38
Issue number	6-8
DOIs	https://doi.org/10.1016/S0026-2714(98)00115-2
Publication status	Published - 1998

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title = "Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors",

abstract = "This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10\% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.",

author = "\{de Wolf\}, M.A.R.C. and \{De Keukeleire\}, Catherine and \{de Wolf\}, Marc and \{van Hove\}, Hugo and Johan Witters",

year = "1998",

doi = "10.1016/S0026-2714(98)00115-2",

language = "English",

volume = "38",

pages = "1097--1101",

journal = "Microelectronics reliability",

issn = "0026-2714",

publisher = "Elsevier Ltd",

number = "6-8",

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TY - JOUR

T1 - Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

AU - de Wolf, M.A.R.C.

AU - De Keukeleire, Catherine

AU - de Wolf, Marc

AU - van Hove, Hugo

AU - Witters, Johan

PY - 1998

Y1 - 1998

N2 - This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.

AB - This paper presents the Hot Carrier Endurance of a High Voltage (100V) self aligned Floating lateral nDMOS transistor. Based on experimental results, a Safe Operating Area is determined according to maximum 10% shift of electrical parameters within 25 years. Process/Device simulation has been done in order to understand the degradation phenomena based on bulk current. Two points of high Impact Ionization rates have been found : one close to the channel junction but in depth, and the second one in the drift region. This later explains the Hot Carrier Degradation of the Ron parameter observed experimentally.

U2 - 10.1016/S0026-2714(98)00115-2

DO - 10.1016/S0026-2714(98)00115-2

M3 - Article

SN - 0026-2714

VL - 38

SP - 1097

EP - 1101

JO - Microelectronics reliability

JF - Microelectronics reliability

IS - 6-8

ER -

Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors

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