In order to obtain a cost-efficient solution, tasks share resources in a Multi-Processor System-on-Chip. In our architecture, shared resources are run-time scheduled. We show how the effects of Latency-Rate servers, which is a class of run-time schedulers, can be included in a dataflow model. The resulting dataflow model, which can have an arbitrary topology, enables us to provide guarantees on the temporal behaviour of the implementation. Traditionally, the end-to-end behaviour of multiple Latency-Rate servers has been analysed with Latency-Rate analysis, which is a Network Calculus. This paper bridges a gap between Network Calculi and dataflow analysis techniques, since we show that a class of run-time schedulers can now be included in dataflow models, or, from a Network Calculus perspective, that restrictions on the topology of graphs that include run-time scheduling can be removed.
|Place of Publication||Enschede|
|Publisher||Computer Architecture for Embedded Systems (CAES)|
|Number of pages||10|
|Publication status||Published - 30 Jan 2007|
|Name||CTIT Technical Report Series|
|Publisher||Centre for Telematics and Information Technology, University of Twente|
- CAES-EEA: Efficient Embedded Architectures
Wiggers, M. H., Bekooij, M. J. G., Bekooij, M., & Smit, G. J. M. (2007). Modelling Run-Time Arbitration by Latency-Rate Servers in Dataflow Graphs. (CTIT Technical Report Series; No. TR-CTIT-07-65). Enschede: Computer Architecture for Embedded Systems (CAES).