Abstract
In order to obtain a cost-efficient solution, tasks share resources in a Multi-Processor System-on-Chip. In our architecture, shared resources are run-time scheduled. We show how the effects of Latency-Rate servers, which is a class of run-time schedulers, can be included in a dataflow model. The resulting dataflow model, which can have an arbitrary topology, enables us to provide guarantees
on the temporal behaviour of the implementation.
Traditionally, the end-to-end behaviour of multiple Latency-Rate servers has been analysed with Latency-Rate analysis, which is a Network Calculus. This paper bridges a gap between Network Calculi and dataflow analysis techniques, since we show that a class of run-time schedulers can now be included in dataflow models, or, from a Network Calculus perspective, that restrictions on the topology of graphs that include run-time scheduling can be removed.
Original language | English |
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Title of host publication | Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems (SCOPES) |
Editors | H. Falk, P. Marwedel |
Place of Publication | New York |
Publisher | ACM Press |
Pages | 11-22 |
Number of pages | 12 |
DOIs | |
Publication status | Published - 20 Apr 2007 |
Event | 10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007 - Acropolis, Nice, France Duration: 20 Apr 2007 → 20 Apr 2007 Conference number: 10 http://www.scopesconf.org/scopes-07/ |
Publication series
Name | ACM International Conference Proceeding Series |
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Publisher | ACM Press |
Number | P2773 |
Volume | 235 |
Workshop
Workshop | 10th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2007 |
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Abbreviated title | SCOPES |
Country/Territory | France |
City | Nice |
Period | 20/04/07 → 20/04/07 |
Internet address |
Keywords
- EWI-10367
- METIS-242180
- IR-61769
- CAES-EEA: Efficient Embedded Architectures