The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult. However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and the specification can be animated, providing a simulator. This paper proposes a high level structural operational semantic (S.O.S.) specification for the class of transport triggered architectures. These architectures are simple, powerful, flexible and modular and can exploit very fine grained parallelism. The S.O.S. is novel in that it follows the structure of the architecture, and by doing so inherits the modularity of the architecture.
|Number of pages||20|
|Publication status||Published - Apr 1997|
|Event||13th IFIP WG 10.5 Conf. on Computer Hardware Description Languages and Their Applications, Toledo, Spain - |
Duration: 1 Jan 1997 → 1 Jan 1997
|Other||13th IFIP WG 10.5 Conf. on Computer Hardware Description Languages and Their Applications, Toledo, Spain|
|Period||1/01/97 → 1/01/97|