Multi-core Architectures and Streaming Applications

Gerardus Johannes Maria Smit, Andre B.J. Kokkeler, P.T. Wolkotte, M.D. van de Burgwal

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    17 Citations (Scopus)
    112 Downloads (Pure)

    Abstract

    In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure fits well to future process technologies, more cores will be available in advanced process technologies, but the complexity per core does not increase, (3) the multi-core concept is fault tolerant, faulty cores can be discarded and (4) multiple cores can be configured fast in parallel. Because in our approach processing and memory are combined in the cores, tasks can be executed efficiently on cores (locality of reference). There are a number of application domains that can be considered as streaming DSP applications: for example wireless baseband processing (for HiperLAN/2, WiMax, DAB, DRM, and DVB), multimedia processing (e.g. MPEG, MP3 coding/decoding), medical image processing, colour image processing, sensor processing (e.g. remote surveillance cameras) and phased array radar systems. In this paper the key characteristics of streaming DSP applications are highlighted, and the characteristics of the processing architectures to efficiently support these types of applications are addressed. We present the initial results of the Annabelle chip that we designed with our approach.
    Original languageUndefined
    Title of host publicationProceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008)
    EditorsI. Mandoiu, A. Kennings
    Place of PublicationNew York, NY, USA
    PublisherAssociation for Computing Machinery (ACM)
    Pages35-42
    Number of pages8
    ISBN (Print)978-1-59593-918-0
    DOIs
    Publication statusPublished - Apr 2008
    EventTenth International Workshop on System-Level Interconnect Prediction, SLIP 2008 - Newcastle, UK
    Duration: 5 Apr 20086 Apr 2008

    Publication series

    Name
    PublisherACM
    Number4952

    Workshop

    WorkshopTenth International Workshop on System-Level Interconnect Prediction, SLIP 2008
    Period5/04/086/04/08
    Other5-6 April 2008

    Keywords

    • EC Grant Agreement nr.: FP6/001908
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-250944
    • EWI-12260
    • IR-64715

    Cite this