Multi-FPGA evaluation platform for disaggregated computing

Dimitris Theodoropoulos; Nikolaos Alachiotis; Dionisios Pnevmatikatos

doi:10.1109/FCCM.2017.20

Multi-FPGA evaluation platform for disaggregated computing

Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios Pnevmatikatos

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

7 Citations (Scopus)

Abstract

We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.

Original language	English
Title of host publication	Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	193
Number of pages	1
ISBN (Electronic)	978-1-5386-4037-1
ISBN (Print)	978-1-5386-4038-8
DOIs	https://doi.org/10.1109/FCCM.2017.20
Publication status	Published - 30 Jun 2017
Externally published	Yes
Event	25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017 - Napa, United States Duration: 30 Apr 2017 → 2 May 2017 Conference number: 25

Conference

Conference	25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017
Abbreviated title	FCCM 2017
Country/Territory	United States
City	Napa
Period	30/04/17 → 2/05/17

Keywords

Disaggregated computing
FPGAs
High-speed interconnect

Access to Document

10.1109/FCCM.2017.20

Cite this

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title = "Multi-FPGA evaluation platform for disaggregated computing",

abstract = "We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.",

keywords = "Disaggregated computing, FPGAs, High-speed interconnect",

author = "Dimitris Theodoropoulos and Nikolaos Alachiotis and Dionisios Pnevmatikatos",

note = "Funding Information: Computer Architecture and VLSI Systems Laboratory Institute of Computer Science, Foundation for Research and Technology - Hellas (FORTH) Funding Information: Acknowledgement: This work has been supported in part by EU H2020 ICT project dRedBox, contract #687632. Publisher Copyright: {\textcopyright} 2017 IEEE.; 25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, FCCM 2017 ; Conference date: 30-04-2017 Through 02-05-2017",

year = "2017",

month = jun,

day = "30",

doi = "10.1109/FCCM.2017.20",

language = "English",

isbn = "978-1-5386-4038-8",

pages = "193",

booktitle = "Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017",

publisher = "IEEE",

address = "United States",

}

Theodoropoulos, D, Alachiotis, N & Pnevmatikatos, D 2017, Multi-FPGA evaluation platform for disaggregated computing. in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017., 7966678, IEEE, Piscataway, NJ, pp. 193, 25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Napa, California, United States, 30/04/17. https://doi.org/10.1109/FCCM.2017.20

Multi-FPGA evaluation platform for disaggregated computing. / Theodoropoulos, Dimitris; Alachiotis, Nikolaos; Pnevmatikatos, Dionisios.
Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017. Piscataway, NJ: IEEE, 2017. p. 193 7966678.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Multi-FPGA evaluation platform for disaggregated computing

AU - Theodoropoulos, Dimitris

AU - Alachiotis, Nikolaos

AU - Pnevmatikatos, Dionisios

N1 - Conference code: 25

PY - 2017/6/30

Y1 - 2017/6/30

N2 - We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.

AB - We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.

KW - Disaggregated computing

KW - FPGAs

KW - High-speed interconnect

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U2 - 10.1109/FCCM.2017.20

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M3 - Conference contribution

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SP - 193

BT - Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017

PB - IEEE

CY - Piscataway, NJ

T2 - 25th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017

Y2 - 30 April 2017 through 2 May 2017

ER -

Multi-FPGA evaluation platform for disaggregated computing

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Conference

Keywords

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