Multi-level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection

Barry de Bruin, Kamlesh Singh, Ying Wang, Jos Huisken, Jose Pineda de Gyvez, Henk Corporaal

Research output: Contribution to journalArticleAcademicpeer-review


We present a systematic evaluation and optimization of a complex bio-medical signal processing application on the BrainWave prototype system, targeted towards ambulatory EEG monitoring within a tiny power budget of <1mW. The considered BrainWave processor is completely programmable, while maintaining energy-efficiency by means of a Coarse-Grained Reconfigurable Array (CGRA). This is demonstrated through the mapping and evaluation of a state-of-the-art non-convulsive epileptic seizure detection algorithm, while ensuring real-time operation and seizure detection accuracy. Exploiting the CGRA leads to an energy reduction of 73.1%, compared to a highly tuned software implementation (SW-only). A total of 9 complex kernels were benchmarked on the CGRA, resulting in an average 4.7x speedup and average 4.4x energy savings over highly tuned SW-only implementations. The BrainWave processor is implemented in 28-nm FDSOI technology with 80kB of Foundry-provided SRAM. By exploiting near-threshold computing for the logic and voltage-stacking to minimize on-chip voltage-conversion overhead, additional 15.2% and 19.5% energy savings are obtained, respectively. At the Minimum-Energy-Point (MEP) (223uW, 8MHz) we report a measured state-of-the-art 90.6% system conversion efficiency, while executing the epileptic seizure detection in real-time.

Original languageEnglish
Number of pages14
JournalIEEE Transactions on Biomedical Circuits and Systems
Publication statusPublished - 19 Oct 2021


  • Bio-medical Signal Processing
  • Coarse-Grained Reconfigurable Arrays
  • Electroencephalography
  • Feature extraction
  • Monitoring
  • Non-Convulsive Epileptic Seizure Detection
  • Optimization
  • Real-time systems
  • System-on-chip
  • Time-frequency analysis
  • Ultra-low power architectures
  • Voltage-Stacking


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