Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

Dongyi Liao, FA Foster Dai, Bram Nauta, Eric A.M. Klumperink

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)
    924 Downloads (Pure)


    This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively.
    Original languageEnglish
    Title of host publicationCustom Integrated Circuits Conference 2017 (CICC)
    Place of PublicationPiscataway
    Number of pages4
    ISBN (Electronic)978-1-5090-5191-5
    ISBN (Print)978-1-5090-5192-2
    Publication statusPublished - 2 May 2017
    EventIEEE Custom Integrated Circuits Conference 2017, CICC - Van Zandt Hotel, Austin, United States
    Duration: 30 Apr 20173 May 2017


    ConferenceIEEE Custom Integrated Circuits Conference 2017, CICC
    Abbreviated titleCICC 2017
    CountryUnited States
    Internet address


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