Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

Dongyi Liao; FA Foster Dai; Bram  Nauta; Eric A.M. Klumperink

doi:10.1109/CICC.2017.7993633

Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

Dongyi Liao, FA Foster Dai, Bram Nauta, Eric A.M. Klumperink

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively.

Original language	English
Title of host publication	Custom Integrated Circuits Conference 2017 (CICC)
Place of Publication	Piscataway
Publisher	IEEE
Number of pages	4
ISBN (Electronic)	978-1-5090-5191-5
ISBN (Print)	978-1-5090-5192-2
DOIs	https://doi.org/10.1109/CICC.2017.7993633
Publication status	Published - 2 May 2017
Event	IEEE Custom Integrated Circuits Conference 2017, CICC - Van Zandt Hotel, Austin, United States Duration: 30 Apr 2017 → 3 May 2017 http://ieee-cicc.org/2017/

Conference

Conference	IEEE Custom Integrated Circuits Conference 2017, CICC
Abbreviated title	CICC 2017
Country/Territory	United States
City	Austin
Period	30/04/17 → 3/05/17
Internet address	http://ieee-cicc.org/2017/

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10.1109/CICC.2017.7993633

CICC 2017 Liao, Foster Dai, Nauta, KlumperinkAccepted author version, 648 KB

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@inproceedings{1913198ad9814737ac833757db4db263,

title = "Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking",

abstract = "This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively. ",

author = "Dongyi Liao and Dai, {FA Foster} and Bram Nauta and Klumperink, {Eric A.M.}",

year = "2017",

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booktitle = "Custom Integrated Circuits Conference 2017 (CICC)",

publisher = "IEEE",

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note = "IEEE Custom Integrated Circuits Conference 2017, CICC, CICC 2017 ; Conference date: 30-04-2017 Through 03-05-2017",

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TY - GEN

T1 - Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

AU - Liao, Dongyi

AU - Dai, FA Foster

AU - Nauta, Bram

AU - Klumperink, Eric A.M.

PY - 2017/5/2

Y1 - 2017/5/2

N2 - This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively.

AB - This paper presents a low phase noise sub-sampling PLL (SSPLL) with multi-phase outputs. Automatic soft switching between the sub-sampling phase loop and frequency loop is proposed to improve robustness against perturbations and interferences that may cause a traditional SSPLL to lose lock. A quadrature LC oscillator with capacitive phase interpolation network is employed to generate multi-phase outputs, which are further utilized to achieve fractional-N frequency synthesis. Implemented in a 130nm CMOS technology, the SSPLL chip is able to achieve a measured in-band phase noise of -120 dBc/Hz and a measured integrated jitter of 209 fs at 2.4 GHz, while consuming 27.2 mW with 16 output phases. The measured reference spur and fractional spur level is -72 dBc and -49 dBc, respectively.

U2 - 10.1109/CICC.2017.7993633

DO - 10.1109/CICC.2017.7993633

M3 - Conference contribution

SN - 978-1-5090-5192-2

BT - Custom Integrated Circuits Conference 2017 (CICC)

PB - IEEE

CY - Piscataway

T2 - IEEE Custom Integrated Circuits Conference 2017, CICC

Y2 - 30 April 2017 through 3 May 2017

ER -

Multi-Phase Sub-Sampling Fractional-N PLL with soft loop switching for fast robust locking

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