Multilevel interconnect reliability on the effects of electro-thermomechanical stresses

The study of interconnect reliability has a long history. The technology has advanced by miniaturization, integrating more and more transistors on a single chip. By necessity the interconnect structure has complex architectures, diverse materials and small features. Conventionally, in multilevel interconnects, the conductor lines are embedded in a dielectric matrix and the conductor lines are linked together by vias, fabricated on the silicon die that contains the active devices. Therefore, electromigration, thermomigration and thermomechanical failures are serious reliability concerns for integrated circuits. Multilevel interconnect failures due to very fast thermal cycle stress or the coupling of electromigration with fast temperature cycling or temperature gradients as well as the electromigration failure at vias are topics that are not fully understood. In this thesis, the effect of those failure mechanisms on the interconnect reliability have been investigated