Multiplexing methods for power watermarking

Daniel Ziener*, Florian Baueregger, Jürgen Teich

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

11 Citations (Scopus)

Abstract

In this paper, we present several enhancements to power watermarking that allow to simultaneously transmit and verify multiple signatures. Power watermarking of netlist IP cores for FPGA architectures is used for detecting IP fraud where the signature (watermark) is transmitted over the power supply pins of the FPGA. Many (watermarked) IP cores can be combined in an FPGA design, which raises the question of how multiple signatures can be detected using the same set of pins. As a solution, we propose multiplexing techniques for power side channel communication, so that all watermarked cores inside the FPGA can be identified to establish a proof of authorship. We analyze different multiplexing methods in order to adapt them to power watermarking and provide experimental results with several cores concurrently transmitting signatures.

Original languageEnglish
Title of host publication2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Pages36-41
Number of pages6
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010 - Anaheim, United States
Duration: 13 Jun 201014 Jun 2010

Conference

Conference2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Abbreviated titleHOST 2010
CountryUnited States
CityAnaheim
Period13/06/1014/06/10

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