TY - JOUR
T1 - Nanometer-thin pure boron CVD layers as material barrier to Au or Cu metallization of Si
AU - Shivakumar, D. Thammaiah
AU - Knežević, Tihomir
AU - Nanver, Lis K.
N1 - Springer deal
PY - 2021/3
Y1 - 2021/3
N2 - Metallization layers of aluminum, gold, or copper are shown to be protected from interactions with silicon substrates by thin boron layers grown by chemical-vapor deposition (CVD) at 450 °C. A 3-nm-thick B-layer was studied in detail. It formed the p+-anode region of PureB diodes that have a metallurgic junction depth of zero on n-type Si. The metals were deposited by electron-beam-assisted physical vapor deposition (EBPVD) at room temperature and annealed at temperatures up to 500 °C. In all cases, the B-layer was an effective material barrier between the metal and Si, as verified by practically unchanged PureB diode I–V characteristics and microscopy inspections of the deposited layers. For this result, it was required that the Si surface be clean before B-deposition. Any Si surface contamination was otherwise seen to impede a complete B-coverage giving, sometimes Schottky-like, current increases. For Au, room-temperature interactions with the Si through such pinholes in the B-layer were excessive after the 500 °C anneal.
AB - Metallization layers of aluminum, gold, or copper are shown to be protected from interactions with silicon substrates by thin boron layers grown by chemical-vapor deposition (CVD) at 450 °C. A 3-nm-thick B-layer was studied in detail. It formed the p+-anode region of PureB diodes that have a metallurgic junction depth of zero on n-type Si. The metals were deposited by electron-beam-assisted physical vapor deposition (EBPVD) at room temperature and annealed at temperatures up to 500 °C. In all cases, the B-layer was an effective material barrier between the metal and Si, as verified by practically unchanged PureB diode I–V characteristics and microscopy inspections of the deposited layers. For this result, it was required that the Si surface be clean before B-deposition. Any Si surface contamination was otherwise seen to impede a complete B-coverage giving, sometimes Schottky-like, current increases. For Au, room-temperature interactions with the Si through such pinholes in the B-layer were excessive after the 500 °C anneal.
KW - UT-Hybrid-D
UR - http://www.scopus.com/inward/record.url?scp=85101294463&partnerID=8YFLogxK
U2 - 10.1007/s10854-021-05422-7
DO - 10.1007/s10854-021-05422-7
M3 - Article
AN - SCOPUS:85101294463
SN - 0957-4522
VL - 32
SP - 7123
EP - 7135
JO - Journal of Materials Science: Materials in Electronics
JF - Journal of Materials Science: Materials in Electronics
IS - 6
ER -