Netlist-level IP protection by watermarking for LUT-Based FPGAs

Moritz Schmid*, Daniel Ziener, Jürgen Teich

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

37 Citations (Scopus)

Abstract

This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the intellectual property core. Converting functional LUTs to LUT-based RAMs or shift registers prevents deletion due to optimization. With this technique, we take watermark carrying components out of the scope of optimization algorithms to achieve complete transparency towards development environments. We can extract the marks from the bitfile of an FPGA. The method was tested on a Xil-inx Virtex-II Pro FPGA and showed low overhead in terms of timing and resources at a reasonable number of watermarked cells.

Original languageEnglish
Title of host publication2008 International Conference on Field-Programmable Technology, ICFPT 2008
Pages209-216
Number of pages8
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventInternational Conference on Field-Programmable Technology, ICFPT 2008 - Taipei, Taiwan, Province of China
Duration: 7 Dec 200810 Dec 2008

Conference

ConferenceInternational Conference on Field-Programmable Technology, ICFPT 2008
Abbreviated titleICFPT 2008
CountryTaiwan, Province of China
CityTaipei
Period7/12/0810/12/08

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    Schmid, M., Ziener, D., & Teich, J. (2008). Netlist-level IP protection by watermarking for LUT-Based FPGAs. In 2008 International Conference on Field-Programmable Technology, ICFPT 2008 (pp. 209-216). [4762385] https://doi.org/10.1109/FPT.2008.4762385