Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs

Kevin Böhmer*, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis, Marco Ottavi

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Highly reliable and customizable micro-processors are critical enablers for future intelligent space platforms. From an architectural point of view, the RISC-V architecture is the current best option for adaptability, with its modular ISA and a multitude of contributors. To implement such a processor at a low price range, companies are looking at reprogrammable Field-Programmable Gate Arrays (FPGAs), which can extend the mission lifetime. SRAM FPGAs are known to be susceptible to low Linear Energy Transfer Single-Event Upsets (SEUs) in the configuration memory, Flash FPGAs on the other hand, are in general immune to such errors. This paper performs for the first time characterization of the open-core NEORV32, a lightweight yet representative RISC-V SoC, and provides insights into the tradeoffs of protection mechanisms against neutron-induced SEUs when this core is implemented in a Flash-based FPGA. The Unmodified core is compared against an ECC-protected version and a register-level TMR with an ECC version. All versions execute the CoreMark benchmark. We show how the addition of ECC protection single-handedly resulted in a more reliable core.

Original languageEnglish
Title of host publication36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
EditorsLuca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
Place of PublicationPiscataway, NJ
PublisherIEEE
ISBN (Electronic)9798350315004
DOIs
Publication statusPublished - 14 Nov 2023
Event36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 - Antipolis, at the Palais des Congrès d'Antibes, Juan-Les-Pins, France
Duration: 3 Oct 20235 Oct 2023

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume36
ISSN (Print)2576-1501
ISSN (Electronic)2765-933X

Conference

Conference36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Abbreviated titleDFT 2023
Country/TerritoryFrance
CityJuan-Les-Pins
Period3/10/235/10/23

Keywords

  • Fault Tolerance
  • Flash-based FPGA
  • NEORV32
  • Radiation Testing
  • Redundancy
  • RISC-V
  • Soft-Processor
  • NLA

Fingerprint

Dive into the research topics of 'Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs'. Together they form a unique fingerprint.

Cite this