Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs

Highly reliable and customizable micro-processors are critical enablers for future intelligent space platforms. From an architectural point of view, the RISC-V architecture is the current best option for adaptability, with its modular ISA and a multitude of contributors. To implement such a processor at a low price range, companies are looking at reprogrammable Field-Programmable Gate Arrays (FPGAs), which can extend the mission lifetime. SRAM FPGAs are known to be susceptible to low Linear Energy Transfer Single-Event Upsets (SEUs) in the configuration memory, Flash FPGAs on the other hand, are in general immune to such errors. This paper performs for the first time characterization of the open-core NEORV32, a lightweight yet representative RISC-V SoC, and provides insights into the tradeoffs of protection mechanisms against neutron-induced SEUs when this core is implemented in a Flash-based FPGA. The Unmodified core is compared against an ECC-protected version and a register-level TMR with an ECC version. All versions execute the CoreMark benchmark. We show how the addition of ECC protection single-handedly resulted in a more reliable core.