New drain current model for nano-meter MOS transistors on-chip threshold voltage test

J. Wan, Hans G. Kerkhoff

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    Traditional reliability tests use complicated equipment, like probe stations and semiconductor parameter analyzers, to measure changes in transistors' threshold voltages, which are both expensive and time consuming. This paper provides an idea to test the threshold voltage with existing low-to-moderate accuracy ADCs and DACs inside SoCs. To avoid the low-accuracy limitation of measurement results, a new MOS model for the nano-meter MOS transistor drain current is proposed. This model only uses six parameters and is valid for all regimes, being the sub-threshold/weak-inversion, moderate-inversion, strong-inversion and linear regime. Measurement results from 90nm transistors and simulation results from 65nm BSIM4.6 models are used to validate the new model. Finally, an on-chip threshold test for reliability purpose is proposed and long-time stress measurement for 90nm PMOS transistors are shown.
    Original languageUndefined
    Title of host publication20th IEEE European Test Symposium, ETS 2015
    Place of PublicationUSA
    Number of pages6
    ISBN (Print)978-1-4799-7603-4
    Publication statusPublished - 25 May 2015
    Event20th IEEE European Test Symposium, ETS 2015 - Grand Hotel Italia, Cluj Napoca, Romania
    Duration: 25 May 201529 May 2015
    Conference number: 20

    Publication series

    PublisherIEEE Computer Society


    Conference20th IEEE European Test Symposium, ETS 2015
    Abbreviated titleETS
    CityCluj Napoca


    • EWI-26295
    • IR-97826
    • METIS-312716
    • CAES-TDT: Testable Design and Test

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