New Methods for Building-In and Improvement of Integrated Circuit Reliability

J.A. van der Pol, Jacob Antonius van der Pol

    Research output: ThesisPhD Thesis - Research external, graduation UT

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    Over the past 30 years the reliability of semiconductor products has improved by a factor of 100 while at the same time the complexity of the circuits has increased by a factor 105. This 7-decade reliability improvement has been realised by implementing a sophisticated reliability assurance system in process development, product development and high volume manufacturing, aimed at building-in product reliability and establishing effective improvement feedback loops in both development and production as described in chapter 1. This thesis deals with new methods that have been developed to continue the current improvement rate also in the new millennium. In process development the adoption of highly accelerated stress techniques (preferably on wafer level) has become crucial as this gives the opportunity to simulate 10 years of product lifetime within a few hours or days, in-line with today’s development cycle times.
    Original languageUndefined
    • Verweij, J.F., Supervisor
    • Kuper, F.G., Supervisor
    • Verweij, J.F., Supervisor
    Award date8 Jun 2000
    Place of PublicationEnschede
    Print ISBNs9036514614
    Publication statusPublished - 8 Jun 2000


    • IR-14106
    • METIS-111451

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