Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM

P.T. Wolkotte, M.D. van de Burgwal, Gerardus Johannes Maria Smit

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    Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.
    Original languageUndefined
    Title of host publicationProceedings of the International Symposium on System-on-Chip (SoC 2006)
    EditorsJ. Nurmi, J. Takala
    Place of PublicationPiscataway, NJ, USA
    PublisherIEEE Computer Society
    Number of pages4
    ISBN (Print)1-4244-0621-8
    Publication statusPublished - Nov 2006
    EventInternational Symposium on System-on-Chip (SoC 2006), Tampere, Finland: Proceedings of the International Symposium on System-on-Chip (SoC 2006) - Piscataway, NJ, USA
    Duration: 13 Nov 200616 Nov 2006

    Publication series

    PublisherIEEE Computer Society


    ConferenceInternational Symposium on System-on-Chip (SoC 2006), Tampere, Finland
    CityPiscataway, NJ, USA


    • EC Grant Agreement nr.: FP6/001908
    • IR-66563
    • EWI-7963
    • CAES-EEA: Efficient Embedded Architectures
    • METIS-238270

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