Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM

P.T. Wolkotte; M.D. van de Burgwal; Gerardus Johannes Maria Smit

doi:10.1109/ISSOC.2006.321993

Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM

P.T. Wolkotte, M.D. van de Burgwal, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.

Original language	Undefined
Title of host publication	Proceedings of the International Symposium on System-on-Chip (SoC 2006)
Editors	J. Nurmi, J. Takala
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE Computer Society
Pages	167-170
Number of pages	4
ISBN (Print)	1-4244-0621-8
DOIs	https://doi.org/10.1109/ISSOC.2006.321993
Publication status	Published - Nov 2006
Event	International Symposium on System-on-Chip (SoC 2006), Tampere, Finland: Proceedings of the International Symposium on System-on-Chip (SoC 2006) - Piscataway, NJ, USA Duration: 13 Nov 2006 → 16 Nov 2006

Publication series

Name
Publisher	IEEE Computer Society
Number	06EX1521

Conference

Conference	International Symposium on System-on-Chip (SoC 2006), Tampere, Finland
City	Piscataway, NJ, USA
Period	13/11/06 → 16/11/06

Keywords

EC Grant Agreement nr.: FP6/001908
IR-66563
EWI-7963
CAES-EEA: Efficient Embedded Architectures
METIS-238270

Access to Document

10.1109/ISSOC.2006.321993

Cite this

@inproceedings{b4b6e34016f944e28c2838f9bd97d96a,

title = "Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM",

abstract = "Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.",

keywords = "EC Grant Agreement nr.: FP6/001908, IR-66563, EWI-7963, CAES-EEA: Efficient Embedded Architectures, METIS-238270",

author = "P.T. Wolkotte and {van de Burgwal}, M.D. and Smit, {Gerardus Johannes Maria}",

note = "Imported from CHAMELEON.xml; null ; Conference date: 13-11-2006 Through 16-11-2006",

year = "2006",

month = nov,

doi = "10.1109/ISSOC.2006.321993",

language = "Undefined",

isbn = "1-4244-0621-8",

publisher = "IEEE Computer Society",

number = "06EX1521",

pages = "167--170",

editor = "J. Nurmi and J. Takala",

booktitle = "Proceedings of the International Symposium on System-on-Chip (SoC 2006)",

address = "United States",

}

Wolkotte, PT, van de Burgwal, MD & Smit, GJM 2006, Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM. in J Nurmi & J Takala (eds), Proceedings of the International Symposium on System-on-Chip (SoC 2006). IEEE Computer Society, Piscataway, NJ, USA, pp. 167-170, International Symposium on System-on-Chip (SoC 2006), Tampere, Finland, Piscataway, NJ, USA, 13/11/06. https://doi.org/10.1109/ISSOC.2006.321993

Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM. / Wolkotte, P.T.; van de Burgwal, M.D.; Smit, Gerardus Johannes Maria.

Proceedings of the International Symposium on System-on-Chip (SoC 2006). ed. / J. Nurmi; J. Takala. Piscataway, NJ, USA : IEEE Computer Society, 2006. p. 167-170.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUM

AU - Wolkotte, P.T.

AU - van de Burgwal, M.D.

AU - Smit, Gerardus Johannes Maria

N1 - Imported from CHAMELEON.xml

PY - 2006/11

Y1 - 2006/11

N2 - Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.

AB - Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.

KW - EC Grant Agreement nr.: FP6/001908

KW - IR-66563

KW - EWI-7963

KW - CAES-EEA: Efficient Embedded Architectures

KW - METIS-238270

U2 - 10.1109/ISSOC.2006.321993

DO - 10.1109/ISSOC.2006.321993

M3 - Conference contribution

SN - 1-4244-0621-8

SP - 167

EP - 170

BT - Proceedings of the International Symposium on System-on-Chip (SoC 2006)

A2 - Nurmi, J.

A2 - Takala, J.

PB - IEEE Computer Society

CY - Piscataway, NJ, USA

Y2 - 13 November 2006 through 16 November 2006

ER -