Coarse−grained reconfigurable architectures, like the Montium, have proven to be a successful approach for low−power and high−performance computation of regular DSP algorithms. The main research question posed in this paper is: Can such architectures also take over less regular algorithms from general purpose processors? This paper presents the implementation of non−power−of−two Fast Fourier Transforms (FFT) to discover the limitations and flexibility of the Montium. The results of the implementation show a order of magnitude reduction of the processing time and energy consumption compared to an ARM processor. Furthermore, we show the accuracy and flexibility of the implementation.
|Publisher||IEEE Computer Society|
|Conference||International Symposium on System-on-Chip (SoC 2006), Tampere, Finland|
|City||Piscataway, NJ, USA|
|Period||13/11/06 → 16/11/06|
- EC Grant Agreement nr.: FP6/001908
- CAES-EEA: Efficient Embedded Architectures