Abstract
Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation.
Original language | English |
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Article number | 10.1155/2009/678045 |
Pages (from-to) | 678045 |
Number of pages | 12 |
Journal | International journal on reconfigurable computing |
Volume | 2009 |
Issue number | 10.1155/2009/678045 |
DOIs | |
Publication status | Published - 2009 |
Keywords
- CAES-EEA: Efficient Embedded Architectures
- EC Grant Agreement nr.: FP6/001908
- IR-68162
- METIS-264424
- EWI-16085