Novel algorithm and architectures for high-speed low-power ConText-based steganography

Least Significant Bit (LSB) insertion method is a popular type of steganographic algorithms in spatial domain. Nevertheless, in this approach essential measures should be considered to enhance the both visual quality and security properties. ConText is a revised version of LSB method to hide secret information in image carrier with enhanced visual imperceptibility. This paper introduces a novel algorithm based on ConText, called the Modified ConText (MCT). The proposed algorithm is based on using a threshold level to compare pixels in a sub-block which leads to faster and power efficient implementation. We strengthen the ConText algorithm which can embed data in a more noisy-like area to increase security and visual quality. Moreover, a high-speed hardware implementation of the MCT algorithm is also presented by employing faster comparisons. In addition to assigning threshold value that can lead to a more efficient architecture, the pre-computation low-power technique is also employed to reduce power consumption. The proposed architecture is synthesized by the ISE tool and implemented on a Spartan-3 FPGA device. The results imply that the proposed architecture outperforms the system frequency, the usage of FPGA resources, and power consumption by approximately 7%, 30%, and 64%, respectively.