TY - JOUR
T1 - Novel low-temperature processing of low noise SDDs with on-detector electronics
AU - Šonský, J.
AU - Koornneef, R.
AU - Huizenga, J.
AU - Hollander, R. W.
AU - Nanver, L. K.
AU - Scholtes, T.
AU - Roozeboom, F.
AU - Van Eijk, C. W.E.
PY - 2004/1/21
Y1 - 2004/1/21
N2 - We have developed a fabrication process (SMART700° process) for monolithic integration of p-channel JFETs and silicon detectors. Processing steps of the SMART700° do not exceed 700°C. The integrated p-JFET has a minimum gate length of 1 μm. A relatively large width can be chosen to achieve a reasonable transconductance, while the JFET capacitance still matches the small capacitance of a detector. The feedback capacitor was also realized on-chip as a double-metal capacitor. In this paper we describe DC and noise characteristics of a silicon drift detector (SDD) with a p-JFET (W/L = 100/1) and a feedback capacitor integrated in the read-out anode (smart-SDD). The device has a transconductance of 1-3 mS, a top gate capacitance of ∼140 fF and a low leakage current (<10 nA/cm2 at room temperature). The smart-SDD with an active area of 3.8 mm2 has reached an energy resolution of ∼50 rms electrons at a temperature of 213 K. This relatively poor energy resolution is due to generation-recombination noise caused by defects produced by a deep n-implantation. Rapid thermal annealing (RTA) and excimer laser annealing (ELA) techniques are experimented to remove the implantation damage. The noise of p-JFETs annealed with RTA and ELA is also presented.
AB - We have developed a fabrication process (SMART700° process) for monolithic integration of p-channel JFETs and silicon detectors. Processing steps of the SMART700° do not exceed 700°C. The integrated p-JFET has a minimum gate length of 1 μm. A relatively large width can be chosen to achieve a reasonable transconductance, while the JFET capacitance still matches the small capacitance of a detector. The feedback capacitor was also realized on-chip as a double-metal capacitor. In this paper we describe DC and noise characteristics of a silicon drift detector (SDD) with a p-JFET (W/L = 100/1) and a feedback capacitor integrated in the read-out anode (smart-SDD). The device has a transconductance of 1-3 mS, a top gate capacitance of ∼140 fF and a low leakage current (<10 nA/cm2 at room temperature). The smart-SDD with an active area of 3.8 mm2 has reached an energy resolution of ∼50 rms electrons at a temperature of 213 K. This relatively poor energy resolution is due to generation-recombination noise caused by defects produced by a deep n-implantation. Rapid thermal annealing (RTA) and excimer laser annealing (ELA) techniques are experimented to remove the implantation damage. The noise of p-JFETs annealed with RTA and ELA is also presented.
KW - Generation-recombination noise
KW - JFET
KW - Low-temperature processing
KW - Rapid thermal annealing
KW - Silicon drift detector
UR - http://www.scopus.com/inward/record.url?scp=0347599189&partnerID=8YFLogxK
U2 - 10.1016/j.nima.2003.09.040
DO - 10.1016/j.nima.2003.09.040
M3 - Article
AN - SCOPUS:0347599189
VL - 517
SP - 301
EP - 312
JO - Nuclear instruments & methods in physics research. Section A : Accelerators, spectrometers, detectors and associated equipment
JF - Nuclear instruments & methods in physics research. Section A : Accelerators, spectrometers, detectors and associated equipment
SN - 0168-9002
IS - 1-3
ER -