Novel technique for reliability testing of silicon integrated circuits

P. Le Minh, Hans Wallinga, P.H. Woerlee, Albert van den Berg, J. Holleman

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.
Original languageEnglish
Title of host publicationProceedings of SPIE conference on MEMS and Microelectronics. 4406
Place of PublicationEdinburgh, UK
PublisherSOIE
Pages185-190
Number of pages6
ISBN (Print)0-8194-4107-4
Publication statusPublished - 2001

Publication series

NameProceedings of SPIE
Volume4406
ISSN (Print)0277-786X

Fingerprint

photoresists
integrated circuits
silicon
reliability analysis
very large scale integration
products
proximity
capacitors
light sources
breakdown
silicon dioxide
decomposition
dosage
high resolution
photons
energy

Keywords

  • METIS-200336
  • IR-42082

Cite this

Le Minh, P., Wallinga, H., Woerlee, P. H., van den Berg, A., & Holleman, J. (2001). Novel technique for reliability testing of silicon integrated circuits. In Proceedings of SPIE conference on MEMS and Microelectronics. 4406 (pp. 185-190). (Proceedings of SPIE; Vol. 4406). Edinburgh, UK: SOIE.
Le Minh, P. ; Wallinga, Hans ; Woerlee, P.H. ; van den Berg, Albert ; Holleman, J. / Novel technique for reliability testing of silicon integrated circuits. Proceedings of SPIE conference on MEMS and Microelectronics. 4406. Edinburgh, UK : SOIE, 2001. pp. 185-190 (Proceedings of SPIE).
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Le Minh, P, Wallinga, H, Woerlee, PH, van den Berg, A & Holleman, J 2001, Novel technique for reliability testing of silicon integrated circuits. in Proceedings of SPIE conference on MEMS and Microelectronics. 4406. Proceedings of SPIE, vol. 4406, SOIE, Edinburgh, UK, pp. 185-190.

Novel technique for reliability testing of silicon integrated circuits. / Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

Proceedings of SPIE conference on MEMS and Microelectronics. 4406. Edinburgh, UK : SOIE, 2001. p. 185-190 (Proceedings of SPIE; Vol. 4406).

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AB - We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon dioxide capacitors of 5 X 5 and 10 X 10 micrometer2 in sizes. Both positive and quasi-negative photoresists were employed. The resultant products are holes in the developed positive photoresist layer and mushroom- shaped spots in the quasi-negative one. Based on the photoresist decomposition energy dose, we could approximately calculate the light emitting power in the near UV range. Due to the proximity between the layer and the light source, the power is interpreted on a more accurate basis, which was a difficult task in previous research. The product sizes, dependent on the light emitting currents and exposure time, establish the core for a rough model that can be used for further application of this technique as a reliability analysis tool. One potential application is to detect and characterize regions of hot carriers on a VLSI circuit under operation for design improvement purpose.

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Le Minh P, Wallinga H, Woerlee PH, van den Berg A, Holleman J. Novel technique for reliability testing of silicon integrated circuits. In Proceedings of SPIE conference on MEMS and Microelectronics. 4406. Edinburgh, UK: SOIE. 2001. p. 185-190. (Proceedings of SPIE).