Novel test structures for dedicated temperature budget determination

Erik Jouwert Faber; Robertus A.M. Wolters; Jurriaan Schmitz

doi:10.1109/TSM.2012.2202793

Novel test structures for dedicated temperature budget determination

Erik Jouwert Faber, Robertus A.M. Wolters, Jurriaan Schmitz

Research output: Contribution to journal › Article › Academic › peer-review

4 Citations (Scopus)

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Abstract

We present a novel method for determining the temperature budget of the process side of silicon substrates and chips, based on well-known silicide formation reactions of metal–Si systems and (four-point probe) resistance measurements. In this paper, we focus on the Pd–Si system that is most temperature sensitive in the range from 100 °C to 200 °C. A variety of test structures is introduced to exploit the specific properties of the diffusion-limited reaction between Pd and Si. Among others, this resulted in gap-based layouts that facilitate an extension of the temperature range to 350 °C. Designs and measurement results are presented, indicating the practicality and the robustness of the proposed technique.

Original language	Undefined
Pages (from-to)	339-345
Number of pages	7
Journal	IEEE transactions on semiconductor manufacturing
Volume	25
Issue number	3
DOIs	https://doi.org/10.1109/TSM.2012.2202793
Publication status	Published - 1 Aug 2012

Keywords

EWI-22224
Metallization
Silicon on insulator technology
IR-81449
process monitoring
METIS-287995
Temperature measurement

Access to Document

10.1109/TSM.2012.2202793

http://eprints.eemcs.utwente.nl/secure2/22224/01/tsm_faber.pdf

Cite this

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title = "Novel test structures for dedicated temperature budget determination",

abstract = "We present a novel method for determining the temperature budget of the process side of silicon substrates and chips, based on well-known silicide formation reactions of metal–Si systems and (four-point probe) resistance measurements. In this paper, we focus on the Pd–Si system that is most temperature sensitive in the range from 100 °C to 200 °C. A variety of test structures is introduced to exploit the specific properties of the diffusion-limited reaction between Pd and Si. Among others, this resulted in gap-based layouts that facilitate an extension of the temperature range to 350 °C. Designs and measurement results are presented, indicating the practicality and the robustness of the proposed technique.",

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AU - Faber, Erik Jouwert

AU - Wolters, Robertus A.M.

AU - Schmitz, Jurriaan

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PY - 2012/8/1

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N2 - We present a novel method for determining the temperature budget of the process side of silicon substrates and chips, based on well-known silicide formation reactions of metal–Si systems and (four-point probe) resistance measurements. In this paper, we focus on the Pd–Si system that is most temperature sensitive in the range from 100 °C to 200 °C. A variety of test structures is introduced to exploit the specific properties of the diffusion-limited reaction between Pd and Si. Among others, this resulted in gap-based layouts that facilitate an extension of the temperature range to 350 °C. Designs and measurement results are presented, indicating the practicality and the robustness of the proposed technique.

AB - We present a novel method for determining the temperature budget of the process side of silicon substrates and chips, based on well-known silicide formation reactions of metal–Si systems and (four-point probe) resistance measurements. In this paper, we focus on the Pd–Si system that is most temperature sensitive in the range from 100 °C to 200 °C. A variety of test structures is introduced to exploit the specific properties of the diffusion-limited reaction between Pd and Si. Among others, this resulted in gap-based layouts that facilitate an extension of the temperature range to 350 °C. Designs and measurement results are presented, indicating the practicality and the robustness of the proposed technique.

KW - EWI-22224

KW - Metallization

KW - Silicon on insulator technology

KW - IR-81449

KW - process monitoring

KW - METIS-287995

KW - Temperature measurement

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DO - 10.1109/TSM.2012.2202793

M3 - Article

SN - 0894-6507

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SP - 339

EP - 345

JO - IEEE transactions on semiconductor manufacturing

JF - IEEE transactions on semiconductor manufacturing

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