Novel test structures for temperature budget determination during wafer processing

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)
37 Downloads (Pure)

Abstract

Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100-200°C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.
Original languageUndefined
Title of host publicationIEEE International Conference on Microelectronic Test Structures (ICMTS), 2010
Place of PublicationPiscataway
PublisherIEEE Computer Society
Pages30-33
Number of pages4
ISBN (Print)978-1-4244-6912-3
DOIs
Publication statusPublished - 22 Mar 2010
Event23rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2010 - Hirosjima, Japan
Duration: 22 Mar 201025 Mar 2010
Conference number: 23
http://www.homepages.ed.ac.uk/ajw/ICMTS/prog10.pdf

Publication series

Name
PublisherIEEE Computer Society Press

Conference

Conference23rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2010
Abbreviated titleICMTS
CountryJapan
CityHirosjima
Period22/03/1025/03/10
Internet address

Keywords

  • METIS-270927
  • SC-RID: Radiation Imaging detectors
  • EWI-18182
  • IR-72452

Cite this

Faber, E. J., Wolters, R. A. M., & Schmitz, J. (2010). Novel test structures for temperature budget determination during wafer processing. In IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010 (pp. 30-33). [10.1109/ICMTS.2010.5466867] Piscataway: IEEE Computer Society. https://doi.org/10.1109/ICMTS.2010.5466867
Faber, Erik Jouwert ; Wolters, Robertus A.M. ; Schmitz, Jurriaan. / Novel test structures for temperature budget determination during wafer processing. IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010. Piscataway : IEEE Computer Society, 2010. pp. 30-33
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title = "Novel test structures for temperature budget determination during wafer processing",
abstract = "Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100-200{\^A}°C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.",
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Faber, EJ, Wolters, RAM & Schmitz, J 2010, Novel test structures for temperature budget determination during wafer processing. in IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010., 10.1109/ICMTS.2010.5466867, IEEE Computer Society, Piscataway, pp. 30-33, 23rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2010, Hirosjima, Japan, 22/03/10. https://doi.org/10.1109/ICMTS.2010.5466867

Novel test structures for temperature budget determination during wafer processing. / Faber, Erik Jouwert; Wolters, Robertus A.M.; Schmitz, Jurriaan.

IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010. Piscataway : IEEE Computer Society, 2010. p. 30-33 10.1109/ICMTS.2010.5466867.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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T1 - Novel test structures for temperature budget determination during wafer processing

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N2 - Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100-200°C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.

AB - Temperature is a crucial parameter in many planar technology processing steps. However, the determination of the actual temperature history at the device side of the substrate is not straightforward. We present a novel method for determining the temperature history of the process side of silicon wafers and chips, which is based on well-known silicide formation reactions of metal-Si systems and is determined via (4 point probe) resistance measurements. In this case we explored the Pd-Si system which has a suitable operating range from 100-200°C. We propose a method based on metal layers patterned in different line configurations (using the width and number of the lines as parameters) and anticipate that silicide developments at these structures is geometrically dependent and hence can provide a way for obtaining a refined temperature information. First experiments on bulk Si wafers show that the proposed method yields predictable and stable results.

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Faber EJ, Wolters RAM, Schmitz J. Novel test structures for temperature budget determination during wafer processing. In IEEE International Conference on Microelectronic Test Structures (ICMTS), 2010. Piscataway: IEEE Computer Society. 2010. p. 30-33. 10.1109/ICMTS.2010.5466867 https://doi.org/10.1109/ICMTS.2010.5466867