Abstract
This paper presents two novel ultra-low-voltage (ULV) Single-Edge-Triggered flip-flops (SET-FF) based on the True-Single-Phase-Clocking (TSPC) scheme. By exploiting the TSPC principle, the overall energy efficiency has been improved compared to the traditional flip-flop designs while providing fully static, contention-free functionality to satisfy ULV operation. At 0.5V near-V th level in 65nm bulk CMOS technology, the proposed SET-FFs demonstrate up to 11-45% and 7-20% of energy efficiency at 0% and 100% data activity rates compared to the best known SET-FFs. The proposed SET-FF can safely operate down to 0.24V of supply voltage without corrupting rail-to-rail voltage levels at its internal nodes. The integration of proposed SET-FFs in a 320-bit parallel shift register demonstrated up to 33% of clock network power, 17-39% of register power reductions compared to the state-of-the-art and commercial standard-cells at near-V th level. In addition to these merits, with the aid of parasitic modeling, this paper re-evaluates the vital performance metrics of SET-FFs at near-V th voltage domain, improving their characterization accuracy and enabling the VLSI integration for commercial end-use.
Original language | English |
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Title of host publication | 39th International Conference on Computer Design (ICCD) |
Publisher | IEEE |
Pages | 57-65 |
Number of pages | 9 |
ISBN (Electronic) | 978-1-6654-3219-1 |
ISBN (Print) | 978-1-6654-3220-7 |
DOIs | |
Publication status | Published - 20 Dec 2021 |
Event | IEEE 39th International Conference on Computer Design (ICCD) - online Duration: 24 Oct 2021 → 27 Oct 2021 https://www.iccd-conf.com/ |
Conference
Conference | IEEE 39th International Conference on Computer Design (ICCD) |
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Abbreviated title | ICCD |
Period | 24/10/21 → 27/10/21 |
Internet address |