Our Multi Processor System on Chip (MPSoC) template provides processing tiles that are connected via a network on chip. A processing tile contains a processing unit and a Scratch Pad Memory (SPM). This paper presents the Omphale tool that performs the first step in mapping a job, represented by a task graph, to such an MPSoC, given the SPM sizes as constraints. Furthermore a memory tile is introduced. The result of Omphale is a Cyclo Static DataFlow (CSDF) model and a task graph where tasks communicate via sliding windows that are located in circular buffers. The CSDF model is used to determine the size of the buffers and the communication pattern of the data. A buffer must fit in the SPM of the processing unit that is reading from it, such that low latency access is realized with a minimized number of stall cycles. If a task and its buffer exceed the size of the SPM, the task is examined for additional parallelism or the circular buffer is partly located in a memory tile. This results in an extended task graph that satisfies the SPM size constraints.
|Place of Publication||Enschede|
|Publisher||Centre for Telematics and Information Technology (CTIT)|
|Number of pages||15|
|Publication status||Published - 5 Jul 2007|
|Name||CTIT Technical Report Series|
|Publisher||Centre for Telematics and Information Technology, University of Twente|
- CAES-EEA: Efficient Embedded Architectures
- Task Graph
- Cyclo Static DataFlow model
- Nested Loop Program
- Scratch Pad Memory
- Circular Buffers
Bijlsma, T., Bekooij, M. J. G., Smit, G. J. M., & Jansen, P. G. (2007). Omphale: Streamlining the Communication for Jobs in a Multi Processor System on Chip. (CTIT Technical Report Series; No. LNCS4549/TR-CTIT-07-44). Enschede: Centre for Telematics and Information Technology (CTIT).