On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

X. Zhang, Hans G. Kerkhoff, Bart Vermeulen

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    6 Citations (Scopus)
    36 Downloads (Pure)

    Abstract

    Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.
    Original languageUndefined
    Title of host publicationProceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society
    Pages531-537
    Number of pages7
    ISBN (Print)978-0-7695-4171-6
    DOIs
    Publication statusPublished - 1 Sep 2010
    Event13th EUROMICRO Conference on Digital System Design, DSD 2010: Architectures, Methods and Tools - Lille, France
    Duration: 1 Sep 20103 Sep 2010
    Conference number: 13

    Publication series

    Name
    PublisherIEEE Computer Society

    Conference

    Conference13th EUROMICRO Conference on Digital System Design, DSD 2010
    Abbreviated titleDSD
    CountryFrance
    CityLille
    Period1/09/103/09/10

    Keywords

    • METIS-276088
    • IR-73132
    • Reconfiguration
    • Scan-based test
    • Network on Chip (NoC)
    • EWI-18374
    • EC Grant Agreement nr.: FP7/215881
    • many-core processor
    • test wrapper
    • test access mechanism (TAM)
    • Dependability

    Cite this

    Zhang, X., Kerkhoff, H. G., & Vermeulen, B. (2010). On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. In Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010 (pp. 531-537). Los Alamitos: IEEE Computer Society. https://doi.org/10.1109/DSD.2010.16
    Zhang, X. ; Kerkhoff, Hans G. ; Vermeulen, Bart. / On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010. Los Alamitos : IEEE Computer Society, 2010. pp. 531-537
    @inproceedings{e4ad27d050e0481ab053bd79993dfdd6,
    title = "On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism",
    abstract = "Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.",
    keywords = "METIS-276088, IR-73132, Reconfiguration, Scan-based test, Network on Chip (NoC), EWI-18374, EC Grant Agreement nr.: FP7/215881, many-core processor, test wrapper, test access mechanism (TAM), Dependability",
    author = "X. Zhang and Kerkhoff, {Hans G.} and Bart Vermeulen",
    note = "10.1109/DSD.2010.16",
    year = "2010",
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    Zhang, X, Kerkhoff, HG & Vermeulen, B 2010, On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. in Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010. IEEE Computer Society, Los Alamitos, pp. 531-537, 13th EUROMICRO Conference on Digital System Design, DSD 2010, Lille, France, 1/09/10. https://doi.org/10.1109/DSD.2010.16

    On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. / Zhang, X.; Kerkhoff, Hans G.; Vermeulen, Bart.

    Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010. Los Alamitos : IEEE Computer Society, 2010. p. 531-537.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    AB - Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.

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    BT - Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010

    PB - IEEE Computer Society

    CY - Los Alamitos

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    Zhang X, Kerkhoff HG, Vermeulen B. On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. In Proceedings of the 13th Euromicro Conference on Digital System Design, DSD 2010. Los Alamitos: IEEE Computer Society. 2010. p. 531-537 https://doi.org/10.1109/DSD.2010.16