On device architectures, subthreshold swing, and power consumption of the piezoelectric field-effect transistor (π-FET)

This paper describes the potential of tunable strain in field-effect transistors to boost performance of digital logic. Voltage-controlled strain can be imposed on a semiconductor body by the integration of a piezoelectric material improving transistor performance. In this paper, we derive the relations governing the subthreshold swing in such devices to improve the understanding. Using these relations and considering the mechanical and technological boundary conditions, we discuss possible device architectures that employ this principle. Further, we review the recently published experimental and modeling results of this device, and give analytical estimates of the power consumption.