Abstract
This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation.
Original language | English |
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Title of host publication | Proceedings of the 2010 International Symposium on System-on-Chip |
Place of Publication | Piscataway |
Publisher | IEEE |
Pages | 103-110 |
Number of pages | 8 |
ISBN (Print) | 978-1-4244-8276-4 |
DOIs | |
Publication status | Published - 29 Sept 2010 |
Event | 2010 International Symposium on System-on-Chip, Tampere, Finland: Proceedings of the 2010 International Symposium on System-on-Chip - Piscataway Duration: 29 Sept 2010 → … |
Conference
Conference | 2010 International Symposium on System-on-Chip, Tampere, Finland |
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City | Piscataway |
Period | 29/09/10 → … |
Keywords
- EC Grant Agreement nr.: FP7/215881