On reconfigurable tiled multi-core programming: processing cores evaluation

K.C. Rovers, M.D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerardus Johannes Maria Smit

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

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Abstract

For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.
Original languageUndefined
Title of host publicationProceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)
PublisherSTW
Pages507-514
Number of pages8
ISBN (Print)978-90-73461-62-8
Publication statusPublished - 26 Nov 2009
Event20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009 - Veldhoven, Netherlands
Duration: 26 Nov 200927 Nov 2009
Conference number: 20

Publication series

Name
PublisherTechnology Foundation

Conference

Conference20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009
CountryNetherlands
CityVeldhoven
Period26/11/0927/11/09

Keywords

  • IR-69092
  • METIS-264268
  • Functional Programming
  • Data flow
  • Beam-forming
  • Phased array
  • EWI-17060
  • semantic model
  • hierarchical tiled architecture
  • CAES-EEA: Efficient Embedded Architectures

Cite this

Rovers, K. C., van de Burgwal, M. D., Kuper, J., Kokkeler, A. B. J., & Smit, G. J. M. (2009). On reconfigurable tiled multi-core programming: processing cores evaluation. In Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC) (pp. 507-514). STW.
Rovers, K.C. ; van de Burgwal, M.D. ; Kuper, Jan ; Kokkeler, Andre B.J. ; Smit, Gerardus Johannes Maria. / On reconfigurable tiled multi-core programming: processing cores evaluation. Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). STW, 2009. pp. 507-514
@inproceedings{9cc1f2ab2f3a4e309098d0c582c1f072,
title = "On reconfigurable tiled multi-core programming: processing cores evaluation",
abstract = "For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.",
keywords = "IR-69092, METIS-264268, Functional Programming, Data flow, Beam-forming, Phased array, EWI-17060, semantic model, hierarchical tiled architecture, CAES-EEA: Efficient Embedded Architectures",
author = "K.C. Rovers and {van de Burgwal}, M.D. and Jan Kuper and Kokkeler, {Andre B.J.} and Smit, {Gerardus Johannes Maria}",
year = "2009",
month = "11",
day = "26",
language = "Undefined",
isbn = "978-90-73461-62-8",
publisher = "STW",
pages = "507--514",
booktitle = "Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)",

}

Rovers, KC, van de Burgwal, MD, Kuper, J, Kokkeler, ABJ & Smit, GJM 2009, On reconfigurable tiled multi-core programming: processing cores evaluation. in Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). STW, pp. 507-514, 20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009, Veldhoven, Netherlands, 26/11/09.

On reconfigurable tiled multi-core programming: processing cores evaluation. / Rovers, K.C.; van de Burgwal, M.D.; Kuper, Jan; Kokkeler, Andre B.J.; Smit, Gerardus Johannes Maria.

Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). STW, 2009. p. 507-514.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

TY - GEN

T1 - On reconfigurable tiled multi-core programming: processing cores evaluation

AU - Rovers, K.C.

AU - van de Burgwal, M.D.

AU - Kuper, Jan

AU - Kokkeler, Andre B.J.

AU - Smit, Gerardus Johannes Maria

PY - 2009/11/26

Y1 - 2009/11/26

N2 - For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.

AB - For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.

KW - IR-69092

KW - METIS-264268

KW - Functional Programming

KW - Data flow

KW - Beam-forming

KW - Phased array

KW - EWI-17060

KW - semantic model

KW - hierarchical tiled architecture

KW - CAES-EEA: Efficient Embedded Architectures

M3 - Conference contribution

SN - 978-90-73461-62-8

SP - 507

EP - 514

BT - Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)

PB - STW

ER -

Rovers KC, van de Burgwal MD, Kuper J, Kokkeler ABJ, Smit GJM. On reconfigurable tiled multi-core programming: processing cores evaluation. In Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC). STW. 2009. p. 507-514