For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.
|Title of host publication||Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)|
|Number of pages||8|
|Publication status||Published - 26 Nov 2009|
|Event||20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009 - Veldhoven, Netherlands|
Duration: 26 Nov 2009 → 27 Nov 2009
Conference number: 20
|Conference||20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009|
|Period||26/11/09 → 27/11/09|
- Functional Programming
- Data flow
- Phased array
- semantic model
- hierarchical tiled architecture
- CAES-EEA: Efficient Embedded Architectures
Rovers, K. C., van de Burgwal, M. D., Kuper, J., Kokkeler, A. B. J., & Smit, G. J. M. (2009). On reconfigurable tiled multi-core programming: processing cores evaluation. In Proceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC) (pp. 507-514). STW.