On reconfigurable tiled multi-core programming: processing cores evaluation

K.C. Rovers, M.D. van de Burgwal, Jan Kuper, Andre B.J. Kokkeler, Gerardus Johannes Maria Smit

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    For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has been presented to allow the development of the model for the specification, design and implementation. The semantic model is used for partitioning the application, evaluating the consequences and mapping to an architectures. Design space exploration allows us to adapt the partitioning and mapping to an architecture or visa-versa. With tiled reconfigurable cores as basis for the architecture, this paper explores the different options for processing cores and its suitability with respect to the design flow of the semantic model approach. Trade-offs with respect to granularity depending on flexibility and efficiency allow interesting design evaluations, especially for programability. This work therefore represent an important step forward in the design flow for designing and using multi-core tiled architectures.
    Original languageUndefined
    Title of host publicationProceedings of the 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC)
    Number of pages8
    ISBN (Print)978-90-73461-62-8
    Publication statusPublished - 26 Nov 2009
    Event20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009 - Veldhoven, Netherlands
    Duration: 26 Nov 200927 Nov 2009
    Conference number: 20

    Publication series

    PublisherTechnology Foundation


    Conference20th Annual Workshop on circuits, Systems and Signal Processing, Prorisc 2009


    • IR-69092
    • METIS-264268
    • Functional Programming
    • Data flow
    • Beam-forming
    • Phased array
    • EWI-17060
    • semantic model
    • hierarchical tiled architecture
    • CAES-EEA: Efficient Embedded Architectures

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