On the design of a real-time volume rendering engine

J. Smit, H.J. Wessels, A. van der Horst, M.J. Bentum

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    Abstract

    An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. Both the interpolator and composition circuit are back from production. They have been tested and both complied with our specifications.
    Original languageEnglish
    Title of host publicationProceedings of the Seventh Eurographics Workshop on Graphics Hardware
    Subtitle of host publication5th and 6th September 1992, King's College, Cambridge, UK
    EditorsP.F. Lister
    Place of PublicationCambridge, United Kingdom
    PublisherEurographics Association
    Pages70-76
    Number of pages7
    DOIs
    Publication statusPublished - 7 Sep 1992
    Event7th Eurographics Workshop on Graphics Hardware, EGGH 1992 - King's College, Cambridge, United Kingdom
    Duration: 5 Sep 19926 Sep 1992
    Conference number: 7

    Publication series

    NameEurographics technical report series
    PublisherEurographics Association
    NumberEG 92 HW
    ISSN (Print)1017-4656

    Workshop

    Workshop7th Eurographics Workshop on Graphics Hardware, EGGH 1992
    Abbreviated titleEGGH92
    Country/TerritoryUnited Kingdom
    CityCambridge
    Period5/09/926/09/92

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