On the design of a real-time volume rendering engine

Jaap Smit; H.J. Wessels; A. van der Horst; M.J. Bentum

doi:10.1016/0097-8493(94)00155-R

On the design of a real-time volume rendering engine

Jaap Smit, H.J. Wessels, A. van der Horst, M.J. Bentum

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Abstract

An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. Both the interpolator and composition circuit are back from production. They have been tested and both complied with our specifications.

Original language	English
Pages (from-to)	297-300
Number of pages	4
Journal	Computer graphics
Volume	19
Issue number	2
DOIs	https://doi.org/10.1016/0097-8493(94)00155-R
Publication status	Published - 1995

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abstract = "An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. Both the interpolator and composition circuit are back from production. They have been tested and both complied with our specifications.",

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