Abstract
An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator circuit and a composition circuit, both capable to operate at very high speeds, have been designed for a 1.6 micron VLSI process. Both the interpolator and composition circuit are back from production. They have been tested and both complied with our specifications.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Seventh Eurographics Workshop on Graphics Hardware |
| Subtitle of host publication | 5th and 6th September 1992, King's College, Cambridge, UK |
| Editors | P.F. Lister |
| Place of Publication | Cambridge, United Kingdom |
| Publisher | Eurographics Association |
| Pages | 70-76 |
| Number of pages | 7 |
| DOIs | |
| Publication status | Published - 7 Sept 1992 |
| Event | 7th Eurographics Workshop on Graphics Hardware, EGGH 1992 - King's College, Cambridge, United Kingdom Duration: 5 Sept 1992 → 6 Sept 1992 Conference number: 7 |
Publication series
| Name | Eurographics technical report series |
|---|---|
| Publisher | Eurographics Association |
| Number | EG 92 HW |
| ISSN (Print) | 1017-4656 |
Workshop
| Workshop | 7th Eurographics Workshop on Graphics Hardware, EGGH 1992 |
|---|---|
| Abbreviated title | EGGH92 |
| Country/Territory | United Kingdom |
| City | Cambridge |
| Period | 5/09/92 → 6/09/92 |