On the design of two single event tolerant slave latches for scan delay testing

Y. Lu; F. Lombardi; S. Pontarelli; M. Ottavi

doi:10.1109/DFT.2012.6378202

On the design of two single event tolerant slave latches for scan delay testing

Y. Lu, F. Lombardi, S. Pontarelli, M. Ottavi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

Abstract

This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32 nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISBN (Electronic)	978-1-4673-3044-2
DOIs	https://doi.org/10.1109/DFT.2012.6378202
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012 - Austin, United States Duration: 3 Oct 2012 → 5 Oct 2012

Conference

Conference	2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
Abbreviated title	DFT
Country/Territory	United States
City	Austin
Period	3/10/12 → 5/10/12

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10.1109/DFT.2012.6378202

Cite this

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title = "On the design of two single event tolerant slave latches for scan delay testing",

abstract = "This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32 nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.",

author = "Y. Lu and F. Lombardi and S. Pontarelli and M. Ottavi",

year = "2012",

doi = "10.1109/DFT.2012.6378202",

language = "English",

isbn = "978-1-4673-3043-5",

booktitle = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",

note = "2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, DFT ; Conference date: 03-10-2012 Through 05-10-2012",

}

Lu, Y, Lombardi, F, Pontarelli, S & Ottavi, M 2012, On the design of two single event tolerant slave latches for scan delay testing. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, Texas, United States, 3/10/12. https://doi.org/10.1109/DFT.2012.6378202

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AU - Lombardi, F.

AU - Pontarelli, S.

AU - Ottavi, M.

PY - 2012

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AB - This paper proposes two new slave latches for improving the Single Event Upset (SEU) tolerance of a flipflop in scan delay testing. The two proposed slave latches utilize additional circuitry to increase the critical charge of the flip-flop compared to designs found in the technical literature. The first (second) latch design achieves a 5.6 (2.4) times larger critical charge with 11% (4%) delay and 16 % (9%) power consumption overhead at 32 nm feature size as compared to the best design found in the technical literature. Moreover, it is shown that the proposed slave latches have also superior performance in the presence of a single event with a multiple node upset.

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DO - 10.1109/DFT.2012.6378202

M3 - Conference contribution

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BT - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

T2 - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012

Y2 - 3 October 2012 through 5 October 2012

ER -

On the design of two single event tolerant slave latches for scan delay testing

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